Semiconductor device

ABSTRACT

A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices having aso-called SOI (silicon on insulator) structure in which a semiconductorlayer is provided on an insulating surface.

2. Description of the Related Art

As an alternative to an integrated circuit using a silicon wafer whichis manufactured by thinly slicing a single crystal semiconductor ingot,an integrated circuit using a semiconductor substrate which is referredto as a silicon on insulator (hereinafter also referred to as “SOI”) inwhich a thin single crystal semiconductor layer is provided on aninsulating surface has been developed. The integrated circuit using anSOI substrate has attracted attention as an integrated circuit whichreduces parasitic capacitance between a drain of a transistor and thesubstrate and improves performance of a semiconductor integratedcircuit.

As a method for manufacturing SOI substrates, a hydrogen ionimplantation separation method is known (for example, see Reference 1:Japanese Published Patent Application No. 2000-124092). A hydrogen ionimplantation separation method is a method by which hydrogen ions areimplanted into a silicon wafer to form a microbubble layer at apredetermined depth from the surface, and a thin silicon layer is bondedto another silicon wafer using the microbubble layer as a cleavageplane. In addition to perform heat treatment for separation of thesilicon layer, it is necessary to perform heat treatment in oxidizingatmosphere in order to form an oxide film on the silicon layer and toremove the oxide film, and then to perform heat treatment at 1000 to1300° C. to increase bonding strength.

On the other hand, a semiconductor device in which an insulatingsubstrate such as high heat resistance glass is provided with a siliconlayer is disclosed (e.g., see Reference 2: Japanese Published PatentApplication No. H11-163363). This semiconductor device has a structurein which the entire surface of crystallized glass having a distortionpoint of 750° C. or more is protected by an insulating silicon film, anda silicon layer obtained by a hydrogen ion implantation separationmethod is fixed to the insulating silicon film.

SUMMARY OF THE INVENTION

Microfabrication has been a main element of a technical development roadmap in a field of semiconductor devices, and thus, the field of deviceshas been developed. So far, as the semiconductor devices areminiaturized, higher speed operation can be realized, and thus lowerpower consumption has been achieved.

However, there is a need for achieving higher performance and lowerpower consumption of semiconductor devices without depending only on amicrofabrication technique.

Accordingly, it is an object to achieve higher performance and lowerpower consumption in semiconductor devices having an SOI structure. Inaddition, it is another object to provide semiconductor devicesincluding more highly integrated and higher performance semiconductorelements.

A plurality of semiconductor elements such as field-effect transistorswhich include a semiconductor layer which has been separated from asemiconductor substrate and is bonded to a supporting substrate havingan insulating surface are stacked with a planarization layer interposedtherebetween.

A semiconductor layer in a lower layer and a semiconductor layer in anupper layer which are stacked with a gate insulating layer, aplanarization layer, an insulating layer in the upper layer, and thelike interposed therebetween are electrically connected by a wiringlayer which penetrates the gate insulating layer, the planarizationlayer, and the insulating layer in the upper layer. In the case wherethe semiconductor layer in the lower layer and the semiconductor layerin the upper layer are stacked so as to be overlapped with each other,the wiring layer may be formed to penetrate the semiconductor layer inthe upper layer and to be in contact with the semiconductor layer in thelower layer. If the semiconductor layers are stacked closely so as to beoverlapped with each other, higher integration of the semiconductordevice can be achieved.

High performance semiconductor elements can be stacked; therefore, ahigher integration of the semiconductor device can be achieved.

In formation of a semiconductor element in the upper layer over asemiconductor element in the lower layer, a planarization layer whichcovers the semiconductor element in the lower layer is formed and aninsulating layer which is bonded to a semiconductor layer in the upperlayer is formed over the planarization layer. Therefore, a bond betweenthe semiconductor layer of the semiconductor element in the upper layerand the insulating layer is facilitated, whereby the reliability of thesemiconductor device and the yield can be improved.

In addition, when the semiconductor layers of field-effect transistorsare bonded to different insulating layers, parasitic capacitance betweenthe semiconductor layers of the field-effect transistors or parasiticcapacitance between gate electrode layers of the field-effecttransistors can be reduced.

Since a semiconductor layer which is separated and transferred from asemiconductor substrate is used, a crystal plane orientation and acrystal axis of a channel length direction in the field-effecttransistor can be controlled by selecting an appropriate semiconductorsubstrate.

By employing a crystal plane orientation or a crystal axis with whichmobility of carriers flowing in a channel of the field-effect transistoris increased, the semiconductor device can be operated at higher speed.In addition, low voltage driving becomes possible, and low powerconsumption can be achieved. In other words, the possibility thatcarriers flowing in the channel of the field-effect transistor arescattered by atoms can be reduced, whereby resistance which electronsand holes meet with can be reduced, and performance of the field-effecttransistor can be improved.

In bonding a supporting substrate to the semiconductor layer, a siliconoxide film which is preferably formed of organic silane is formed on oneor both surfaces that are to form a bond and the silicon oxide film canbe used as an insulating layer which is to be bonded to thesemiconductor layer. Examples of organic silane gas that can be used aresilicon-containing compounds such as tetraethoxysilane (TEOS) (chemicalformula: Si(OC₂H₅)₄), trimethylsilane (TMS) (chemical formula:(CH₃)₃SiH), tetramethylsilane (chemical formula: Si(CH₃)₄),tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane(OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (chemical formula:SiH(OC₂H₅)₃), and trisdimethylaminosilane (chemical formula:SiH(N(CH₃)₂)₃). That is, in a structure in which a semiconductor layeris bonded to a supporting substrate, a layer which has a smooth surfaceand forms a hydrophilic surface is provided as a bonding surface.

Note that a chemical vapor deposition (CVD) method in this specificationincludes a plasma CVD method, a thermal CVD method, and a photo CVDmethod.

The silicon oxide film serving as the insulating layer which is to bebonded to the semiconductor layer can be formed by a chemical vapordeposition method using monosilane, disilane, or trisilane as a sourcegas. Further, the silicon oxide film serving as the insulating layerwhich is bonded to the semiconductor layer may be a thermal oxide filmwhich preferably contains chlorine.

The semiconductor layer which is to be bonded to the supportingsubstrate can be obtained by cleavage and release at a fragile layer inthe semiconductor substrate. The fragile layer can be formed byirradiation with ions of hydrogen, helium, or a halogen typified byfluorine. In this case, irradiation may be performed with ions of oneatom or the same kind of atoms with different masses. In the case ofirradiation with hydrogen ions, it is preferable that H⁺, H₂ ⁺, and H₃ ⁺ions be contained and the proportion of H₃ ⁺ ions be high.

The supporting substrate may be provided with a silicon nitride film ora silicon nitride oxide film as a blocking layer (also referred to as abarrier layer) which prevents diffusion of impurity elements. Further, asilicon oxynitride film may be combined as an insulating film which hasa function of relieving stress. Note that a silicon oxynitride filmrefers to a film that contains more oxygen than nitrogen and, in thecase where measurements are performed using Rutherford backscatteringspectrometry (RBS) and hydrogen forward scattering (HFS), includesoxygen, nitrogen, Si, and hydrogen at concentrations ranging from 50 to70 at. %, 0.5 to 15 at. %, 25 to 35 at. %, and 0.1 to 10 at. %,respectively. Further, a silicon nitride oxide film refers to a filmthat contains more nitrogen than oxygen and, in the case wheremeasurements are performed using RBS and HFS, includes oxygen, nitrogen,Si, and hydrogen at concentrations ranging from 5 to 30 at. %, 20 to 55at. %, 25 to 35 at. %, and 10 to 30 at. %, respectively. Note thatpercentages of nitrogen, oxygen, Si, and hydrogen fall within the rangesgiven above, where the total number of atoms contained in the siliconoxynitride film or the silicon nitride oxide film is defined as 100 at.%.

In addition, a protection layer may be formed between the semiconductorsubstrate and the insulating layer which is bonded to the semiconductorlayer. The protection layer can be a single layer or a laminate oflayers selected from a silicon nitride layer, a silicon oxide layer, asilicon nitride oxide layer, or a silicon oxynitride layer. Those layerscan be formed over the semiconductor substrate before the fragile layeris formed in the semiconductor substrate. Alternatively, those layersmay be formed over the semiconductor substrate after the fragile layeris formed in the semiconductor substrate.

A mode of a semiconductor device according to the present invention is asemiconductor device including a plurality of field-effect transistorswhich are stacked with a planarization layer interposed therebetweenover a substrate having an insulating surface, in which semiconductorlayers in the plurality of field-effect transistors are separated fromsemiconductor substrates, and the semiconductor layers are bonded to aninsulating layer formed over the substrate having an insulating surfaceor an insulating layer formed over the planarization layer.

A mode of a semiconductor device according to the present invention is asemiconductor device including a substrate having an insulating surface;a first field-effect transistor having a first semiconductor layer, afirst gate insulating layer, a first gate electrode layer, a firstsource electrode layer, and a first drain electrode layer over thesubstrate having the insulating surface; a planarization layer over thefirst field-effect transistor; and a second field-effect transistorhaving a second semiconductor layer, a second gate insulating layer, asecond gate electrode layer, a second source electrode layer, and asecond drain electrode layer over the planarization layer, which forms astacked structure with the first field-effect transistor and theplanarization layer; in which the first field-effect transistor isbonded to a first insulating layer formed between the firstsemiconductor layer and the substrate having the insulating surface andis provided over the substrate having the insulating surface, and thesecond field-effect transistor is bonded to a second insulating layerprovided over the planarization layer and is provided above the firstfield-effect transistor.

A mode of a semiconductor device according to the present invention is asemiconductor device including a substrate having an insulating surface;a first field-effect transistor having a first semiconductor layer, afirst gate insulating layer, a first gate electrode layer, a firstsource electrode layer, and a first drain electrode layer over thesubstrate having the insulating surface; a planarization layer over thefirst field-effect transistor; and a second field-effect transistorhaving a second semiconductor layer, a second gate insulating layer, asecond gate electrode layer, a second source electrode layer, and asecond drain electrode layer over the planarization layer, which forms astacked structure with the first field-effect transistor and theplanarization layer; in which the first field-effect transistor isbonded to a first insulating layer formed between the firstsemiconductor layer and the substrate having the insulating surface andis provided over the substrate having the insulating surface, the secondfield-effect transistor is bonded to a second insulating layer providedover the planarization layer and is provided above the firstfield-effect transistor, and a crystal plane orientation of the firstsemiconductor layer and a crystal plane orientation of the secondsemiconductor layer are different from each other.

A mode of a semiconductor device according to the present invention is asemiconductor device including a substrate having an insulating surface;a first field-effect transistor having a first semiconductor layer, afirst gate insulating layer, a first gate electrode layer, a firstsource electrode layer, and a first drain electrode layer over thesubstrate having the insulating surface; a planarization layer over thefirst field-effect transistor; and a second field-effect transistorhaving a second semiconductor layer, a second gate insulating layer, asecond gate electrode layer, a second source electrode layer, and asecond drain electrode layer over the planarization layer, which forms astacked structure with the first field-effect transistor and theplanarization layer; in which the first field-effect transistor isbonded to a first insulating layer formed between the firstsemiconductor layer and the substrate having the insulating surface andis provided over the substrate having the insulating surface, the secondfield-effect transistor is bonded to a second insulating layer providedover the planarization layer and is provided above the firstfield-effect transistor, and a crystal plane orientation of the firstsemiconductor layer and a crystal plane orientation of the secondsemiconductor layer are the same, and a crystal axis of a channel lengthdirection of the first semiconductor layer and a crystal axis of achannel length direction of the second semiconductor layer are differentfrom each other.

Note that in the present invention, a semiconductor device refers to adevice which can function by utilizing the semiconductorcharacteristics. According to the present invention, a device having acircuit including semiconductor elements (e.g., transistors, memoryelements, or diodes) or a semiconductor device such as a chip includinga processor circuit can be manufactured.

Higher performance and lower power consumption can be achieved insemiconductor devices having an SOI structure. In addition,semiconductor devices including more highly integrated and higherperformance semiconductor elements can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate semiconductor devices of the presentinvention;

FIGS. 2A and 2B illustrate methods for manufacturing semiconductordevices of the present invention;

FIGS. 3A to 3D illustrate a method for manufacturing a semiconductordevice of the present invention;

FIGS. 4A to 4D illustrate a method for manufacturing a semiconductordevice of the present invention;

FIGS. 5A to 5E illustrate a method for manufacturing a semiconductordevice of the present invention;

FIGS. 6A to 6D illustrate a method for manufacturing a semiconductordevice of the present invention;

FIGS. 7A to 7F illustrate a semiconductor device of the presentinvention;

FIGS. 8A to 8D illustrate a semiconductor device of the presentinvention;

FIG. 9 is a block diagram illustrating a structure of a microprocessorwhich can be obtained employing a semiconductor device of the presentinvention;

FIG. 10 is a block diagram illustrating a structure of an RFCPU whichcan be obtained employing a semiconductor device of the presentinvention;

FIGS. 11A to 11G illustrate application examples of a semiconductordevice of the present invention;

FIG. 12 illustrates a semiconductor device of the present invention;

FIGS. 13A and 13B illustrate semiconductor devices of the presentinvention;

FIGS. 14A to 14C illustrate application examples of a semiconductordevice of the present invention;

FIGS. 15A to 15D illustrate a method for manufacturing a semiconductordevice of the present invention;

FIGS. 16A to 16D illustrate a method for manufacturing a semiconductordevice of the present invention;

FIGS. 17A to 17C illustrate a method for manufacturing a semiconductordevice of the present invention;

FIGS. 18A and 18B illustrate manufacturing apparatuses of asemiconductor device which can be applied to the present invention;

FIG. 19 illustrates a manufacturing apparatus of a semiconductor devicewhich can be applied to the present invention;

FIG. 20 illustrates a manufacturing apparatus of a semiconductor devicewhich can be applied to the present invention;

FIGS. 21A and 21B illustrate semiconductor devices of the presentinvention; and

FIGS. 22A and 22B illustrate semiconductor devices of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment modes of the present invention will be described in detailwith reference to the drawings. Note that the present invention is notlimited to the following description and it will be readily appreciatedby those skilled in the art that modes and details can be modified invarious ways without departing from the spirit and the scope of thepresent invention. Accordingly, the present invention should not beconstrued as being limited to the description of the embodiment modes tobe given below. Note that in a structure of the present inventiondescribed below, like portions or portions having like functions indifferent drawings are denoted by the like reference numerals andrepeated description thereof is omitted.

Embodiment Mode 1

A method for manufacturing a semiconductor device of the presentinvention is described with reference to FIGS. 1A and 1B, FIGS. 2A and2B, FIGS. 3A to 3D, and FIGS. 4A to 4D. This embodiment mode describes acomplementary metal oxide semiconductor (CMOS) as an example ofsemiconductor devices which include more highly integrated and higherperformance semiconductor elements.

In this embodiment mode, semiconductor elements are stacked with aplanarization layer therebetween. The semiconductor elements include asemiconductor layer which is separated from a semiconductor substrateand is bonded to a supporting substrate having an insulating surface. Asingle-crystal semiconductor substrate is preferably used as thesemiconductor substrate, and a single-crystal semiconductor layer ispreferably formed as the semiconductor layer which is separated from thesemiconductor substrate and bonded to the supporting substrate.

FIG. 1A illustrates a semiconductor device of this embodiment mode. Ablocking layer 109, an insulating layer 104, a protection layer 121, afield-effect transistor 230, an insulating layer 210, a planarizationlayer 211, an insulating layer 212, a field-effect transistor 231, aninsulating layer 222, and a planarization layer 223 are formed over asupporting substrate 101 having an insulating surface. The field-effecttransistor 230 and the field-effect transistor 231 are thin filmtransistors which include a thin semiconductor layer. The field-effecttransistor 230 includes a semiconductor layer 119 which includesimpurity regions 208 a and 208 b, which are a source region and a drainregion, and a channel formation region 209, a gate insulating layer 205,and a gate electrode layer 206. The field-effect transistor 231 includesa semiconductor layer 216 which includes impurity regions 220 a and 220b, which are a source region and a drain region, and a channel formationregion 221, a gate insulating layer 217, and a gate electrode layer 218.A wiring layer 226 is formed to be in contact with the impurity region208 b. A wiring layer 224 is formed to be in contact with the impurityregion 220 a. A wiring layer 225 which is formed to be in contact withthe impurity region 208 a and the impurity region 220 b electricallyconnects the field-effect transistor 230 to the field-effect transistor231.

FIG. 1A illustrates an example of a semiconductor device in which thewiring layer 225 and the wiring layer 226 are formed in openings(contact holes) which successively penetrate the gate insulating layer205, the insulating layer 210, the planarization layer 211, theinsulating layer 212, the gate insulating layer 217, the insulatinglayer 222, and the planarization layer 223. FIG. 1B illustrates analternative example of electrical connection between the field-effecttransistor 230 and the field-effect transistor 231.

The wiring layers 224, 225, and 226 have a stacked structure in whichwiring layers 240 a, 240 b, 240 c, and 240 d which are embedded wiringlayers are formed to fill openings which are contact holes and thenwiring layers 241 a, 241 b, and 241 c which are lead wiring layers areformed over the embedded wiring layers. The wiring layers may include abarrier metal film or a seed film in the openings. Wiring layers 233,234, 235, 236, and 237 in FIG. 1B and FIGS. 2A and 2B are wiring layershaving a stacked structure similar to the wiring layers 224, 225, and226.

In the case where a contact hole for forming a wiring layer is formed instacked layers including multiple layers, a side surface of the contacthole may have a plurality of taper angles. For example, in the casewhere an etching process include a plurality of steps which employdifferent etching gasses, taper angles and diameters of the opening maybe varied depending on the etching conditions. FIG. 21A illustrates anexample in which a wiring layer is formed in a contact hole having aplurality of taper angles. In a semiconductor device in FIG. 21A,contact holes in which wiring layers 242 c and 242 d which are embeddedwiring layers of wiring layers 245 and 246 are formed have a firstopening which is formed in the gate insulating layer 205, the insulatinglayer 210, the planarization layer 211, and the insulating layer 212;and a second opening which is formed in the gate insulating layer 217,the insulating layer 222, and the planarization layer 223. The firstopening and the second opening are different in shape and the taperangle of the second opening is larger than that of the first opening.

The wiring layer may include a barrier metal film or a seed film in theopenings. An example in which a barrier metal film is formed isillustrated in FIG. 21B. In a semiconductor device in FIG. 21B, wiringlayers 247, 248, and 249 include barrier metal films 243 a, 243 b, 243c, and 243 d which are in contact with surfaces of contact holes.

A semiconductor device in FIG. 1B is an example in which after theplanarization layer 211 which covers the field-effect transistor 230 isformed, openings which reach the impurity regions 208 a and 208 b areformed in the gate insulating layer 205, the insulating layer 210, andthe planarization layer 211; and wiring layers 234 and 237 which areconnected to the impurity regions 208 a and 208 b, respectively, areformed. The wiring layer 233 which is formed to be in contact with theimpurity region 220 b of the field-effect transistor 231 and the wiringlayer 234 electrically connects the field-effect transistor 231 in theupper layer to the field-effect transistor 230 in the lower layer. Inthe case of FIG. 1B, another planarization layer may be formed over thewiring layers 234 and 237 to planarize projections and depressions dueto the wiring layers 234 and 237 before the insulating layer 212 isformed. In FIG. 1B, the insulating layer 212 is formed to be thick so asto also serve as a planarization layer.

The field-effect transistors which are stacked have either n-type orp-type conductivity. FIG. 1A illustrates an example in which thefield-effect transistor 230 in the lower layer is an n-channelfield-effect transistor which includes n-type impurity regions as theimpurity regions 208 a and 208 b, while the field-effect transistor 231in the upper layer is a p-channel field-effect transistor which includesp-type impurity regions as the impurity regions 220 a and 220 b. On theother hand, FIG. 1B illustrates an example in which the field-effecttransistor 230 in the lower layer is a p-channel field-effect transistorwhich includes p-type impurity regions as the impurity regions 208 a and208 b and the field-effect transistor 231 in the upper layer is ann-channel field-effect transistor which includes n-type impurity regionsas the impurity regions 220 a and 220 b.

A semiconductor layer in a lower layer and a semiconductor layer in anupper layer which are stacked with a gate insulating layer, aplanarization layer, an insulating layer in the upper layer, and thelike interposed therebetween are electrically connected by a wiringlayer which penetrates the gate insulating layer, the planarizationlayer, and the insulating layer in the upper layer. In the case wherethe semiconductor layer in the lower layer and the semiconductor layerin the upper layer are stacked so as to be overlapped with each other,the wiring layer may be formed to penetrate the semiconductor layer inthe upper layer and to be in contact with the semiconductor layer in thelower layer. If the semiconductor layers are stacked closely so as to beoverlapped with each other, higher integration of the semiconductordevice can be achieved.

FIGS. 2A and 2B illustrate semiconductor devices in which thesemiconductor layer in the lower layer and the semiconductor layer inthe upper layer are stacked so as to be overlapped with each other. InFIG. 2A, the semiconductor layer 119 (the impurity region 208 a) in thefield-effect transistor 230 which is the semiconductor element in thelower layer and the semiconductor layer 216 (the impurity region 220 b)in the field-effect transistor 231 which is the semiconductor element inthe upper layer are stacked to as to be overlapped with each other. Thewiring layer 235 which electrically connects the field-effect transistor230 to the field-effect transistor 231 is formed to penetrate the gateinsulating layer 205, the insulating layer 210, the planarization layer211, the insulating layer 212, the semiconductor layer 216 (the impurityregion 220 b), the gate insulating layer 217, the insulating layer 222,and the planarization layer 223 and to reach the semiconductor layer 119(the impurity region 208 a).

While the semiconductor layer 119 in the field-effect transistor 230 andthe semiconductor layer 216 in the field-effect transistor 231 arepartially overlapped with each other in FIG. 2A, they may besubstantially overlapped with each other using the same mask or the likeas illustrated in FIG. 2B. The larger the area in which thesemiconductor layers are overlapped with each other is, the higherintegration can be realized. In the semiconductor device in FIG. 2B, thefield-effect transistor 230 and the field-effect transistor 231 arestacked to be almost completely overlapped with each other with theplanarization layer therebetween. The wiring layer 236 whichelectrically connects the field-effect transistor 230 to thefield-effect transistor 231 is formed to penetrate the gate insulatinglayer 205, the insulating layer 210, the planarization layer 211, theinsulating layer 212, the semiconductor layer 216 (the impurity region220 b), the gate insulating layer 217, the insulating layer 222, and theplanarization layer 223 and to reach the semiconductor layer 119 (theimpurity region 208 b).

Since a semiconductor device of the present invention has a structure inwhich semiconductor elements are stacked three dimensionally and arehighly integrated, the semiconductor elements can be aligned side byside and in contact with one insulating layer or they can be stackedabove and below with a planarization layer interposed therebetween andbe in contact with different insulating layers. Therefore, arrangementflexibility of semiconductor elements in the semiconductor device ishigh, which can lead to further integration and higher performance. As asemiconductor element, not to mention a field-effect transistor, amemory element which uses a semiconductor layer can be employed;accordingly, a semiconductor device which can satisfy functions requiredfor various applications can be manufactured and provided.

Further, since a semiconductor element which includes a semiconductorlayer separated from a semiconductor substrate has smaller leak currentcaused by grain boundaries than a polycrystalline semiconductor layerwhich is obtained by crystallization, low power consumption of thesemiconductor device can be realized. Further, variation in thresholdvalues of semiconductor elements due to variation in crystal orientationis small. In addition, ridges on the semiconductor layer surface due tolaser crystallization can be reduced; therefore, a gate insulating layercan be thinned.

All the field-effect transistors which are stacked may be n-channelfield-effect transistors or may be p-channel field-effect transistors.Alternatively, a plurality of field-effect transistors may be providedto be in contact with one insulating layer and those field-effecttransistors may include both an n-channel field-effect transistor and ap-channel field-effect transistor.

While this embodiment mode describes a laminate of two layers, alaminate of more than two layers may be employed. A plurality ofsemiconductor elements can be stacked by bonding an insulating layerprovided over a planarization layer and an insulating layer providedover a semiconductor layer.

Since a semiconductor layer which is separated and transferred from asemiconductor substrate is used in a semiconductor device of thisembodiment mode, a crystal plane orientation and crystal axes of achannel length direction in the field-effect transistor can becontrolled by selecting a semiconductor substrate.

By employing a crystal orientation or a crystal axis with which mobilityof carriers flowing in a channel of the field-effect transistor isincreased, the semiconductor device can be operated at higher speed. Inaddition, low voltage driving becomes possible, and low powerconsumption can be achieved. In other words, the possibility thatcarriers flowing in the channel of the field-effect transistor arescattered by atoms can be reduced, whereby resistance which electronsand holes meet with can be reduced and performance of the field-effecttransistor can be improved.

Hereinafter, a method for manufacturing a semiconductor device of thisembodiment mode is described with reference to FIGS. 3A to 3D, FIGS. 4Ato 4D, FIGS. 7A to 7F, and FIGS. 8A to 8D.

First, a method for providing a semiconductor layer over a supportingsubstrate having an insulating surface from a semiconductor substrate isdescribed with reference to FIGS. 3A to 3D and FIGS. 4A to 4C.

A semiconductor substrate 108 illustrated in FIG. 3A is cleaned, and thesemiconductor substrate 108 is irradiated with ions that are acceleratedby an electric field so as to reach a given depth from the surface ofthe semiconductor substrate 108 to form a fragile layer 110. Ionirradiation is performed in consideration of the thickness of asemiconductor layer which is to be transferred to a supportingsubstrate. An accelerating voltage for irradiating the semiconductorsubstrate 108 with ions is set in consideration of the thickness.

As the semiconductor substrate 108, a semiconductor substrate such as asilicon substrate or a germanium substrate, or a compound semiconductorsubstrate such as a gallium arsenide substrate or an indium phosphidesubstrate is used. The semiconductor substrate 108 is preferably asingle-crystal semiconductor substrate, but it may be a polycrystallinesemiconductor substrate. Further, a semiconductor substrate formed ofsilicon having a lattice distortion, silicon germanium in whichgermanium is added to silicon, or the like may be used. Silicon having adistortion can be formed by film formation of silicon on silicongermanium or silicon nitride which has a larger lattice constant thansilicon. The semiconductor layer which is provided over the supportingsubstrate can be determined by a semiconductor substrate which isselected to be used as a base.

In addition, the crystal plane orientation of the semiconductorsubstrate 108 may be selected according to a semiconductor element whichis to be formed (a field-effect transistor in this embodiment mode). Forexample, a semiconductor substrate having a {100} crystal planeorientation, a {110} crystal plane orientation, or the like can be used.

In this embodiment mode, an ion irradiation separation method in whichhydrogen, helium, or fluorine is added to the given depth of thesemiconductor substrate by ion irradiation, and then, heat treatment isperformed and a semiconductor layer of a superficial part is separatedis employed; however, a method in which single-crystal silicon isepitaxially grown over porous silicon, and then, a porous silicon layeris cleaved and released with water jet may be employed.

For example, a single-crystal silicon substrate is used as thesemiconductor substrate 108, and the surface thereof is treated withdilute hydrofluoric acid so that a natural oxide film is removed as wellas contaminant such as dust or the like attaching to the surface,whereby the surface of the semiconductor substrate 108 is cleaned.

The fragile layer 110 may be formed by irradiation with ions by anion-doping method or an ion implantation method. The fragile layer 110is formed by irradiating the semiconductor substrate 108 with ions ofhydrogen, helium, or a halogen typified by fluorine. In the case ofirradiation with fluorine ions as a halogen element, BF₃ may be used asa source gas. Note that an ion implantation method refers to a method inwhich a semiconductor is irradiated with an ionized gas on which massseparation is performed.

When the single-crystal silicon substrate is irradiated with halogenions such as fluorine ions by an ion irradiation method, fluorine whichis added knocks out (expels) silicon atoms in silicon crystal lattices,so that blank portions are formed effectively to make microvoids in thefragile layer. In this case, the volume of the microvoids formed in thefragile layer is changed by heat treatment at a relatively lowtemperature, and a thin single-crystal semiconductor layer can be formedby cleavage along the fragile layer. After irradiation with fluorineions, irradiation with hydrogen ions may be performed so that hydrogenmay be included in the voids. Since the cleavage is performed along thefragile layer which is formed to release a thin semiconductor layer fromthe semiconductor substrate by utilization of change in volume of themicrovoids which are formed in the fragile layer, it is preferable toeffectively utilize the action of fluorine ions and hydrogen ions inabove-described manner.

Irradiation may be performed with ions of one atom or the same kindatoms with different masses. For example, in the case of irradiationwith hydrogen ions, it is preferable that H⁺, H₂ ⁺, and H₃ ⁺ ions becontained and the proportion of H₃ ⁺ ions be high. In the case ofirradiation with hydrogen ions, if H⁺, H₂ ⁺, and H₃ ⁺ ions are containedand the proportion of H₃ ⁺ ions is high, irradiation efficiency can beincreased and irradiation time can be shortened. Such a structurefacilitates the release.

Because there is a need for irradiation with ions at a high dose forforming the fragile layer, the surface of the semiconductor substrate108 may be roughened. Therefore, a protection layer against ionirradiation, such as a silicon nitride film, a silicon nitride oxidefilm, or a silicon oxide film may be formed on the surface which isirradiated with ions to have a thickness of from 50 to 200 nm.

For example, a stacked layer of a silicon oxynitride film (with athickness of 5 to 300 nm, preferably 30 to 150 nm (e.g., 50 nm)) and asilicon nitride oxide film (with a thickness of 5 to 150 nm, preferably10 to 100 nm (e.g., 50 nm)) is formed by a plasma CVD method as theprotection layer over the semiconductor substrate 108. As an example, asilicon oxynitride film is formed over the semiconductor substrate 108to have a thickness of 50 nm, and a silicon nitride oxide film is formedthereover to have a thickness of 50 nm. The silicon oxynitride film maybe a silicon oxide film which is manufactured by a chemical vapordeposition method using an organic silane gas.

Further, degreasing and cleaning may be performed on the semiconductorsubstrate 108 and an oxide film on the surface may be removed andthermal oxidation may be performed. As thermal oxidation, general dryoxidation may be performed; however, oxidation in an oxidizingatmosphere to which a halogen is added is preferably performed. Forexample, heat treatment is performed at a temperature of 700° C. orhigher in an atmosphere containing HCl at 0.5 to 10 volume % (preferably3 volume %) with respect to oxygen. The thermal oxidation is preferablyperformed at a temperature of 950 to 1100° C. The processing time may be0.1 to 6 hours, preferably 0.5 to 3.5 hours. The film thickness of theoxide film which is formed is 10 to 1000 nm (preferably, 50 to 200 nm),for example, 100 nm.

As a substance including a halogen, one or more kinds selected from HF,NF₃, HBr, Cl₂, CIF₃, BCl₃, F₂, or Br₂ can be given besides HCl.

When heat treatment is performed within such a temperature range, agettering effect by a halogen element can be obtained. Getteringparticularly has an effect of removing metal impurities. In other words,impurities such as metal are turned into a volatile chloride, moved intothe air, and removed by action of chlorine. The heat treatment iseffective if being carried out on the semiconductor substrate 108 withits surface subjected to chemical mechanical polishing (CMP) treatment.Further, hydrogen has an effect of compensating defects at an interfacebetween the semiconductor substrate 108 and the oxide film which isformed and reducing a local level density of the interface, and theinterface between the semiconductor substrate 108 and the oxide film isinactivated and thus electric characteristics are stabilized.

A halogen can be contained in the oxide film formed by this heattreatment. Halogen elements are contained at a concentration of 1×10¹⁷to 5×10²⁰ atoms/cm³, so that the oxide film can serve as a protectionfilm which captures impurities such as metal and prevents contaminationof the semiconductor substrate 108.

For forming the fragile layer 110, an accelerating voltage and the totalnumber of ions can be adjusted in accordance with the thickness of afilm deposited over the semiconductor substrate, the thickness of thesemiconductor layer which is to be separated from the semiconductorsubstrate and transferred to the supporting substrate, and ion specieswhich are used for irradiation.

For example, a hydrogen gas is used as a material, and irradiation withions is performed at an accelerating voltage of 40 kV with the totalnumber of ions of 2×10¹⁶ ions/cm² by an ion doping method so that thefragile layer can be formed. If the thickness of the protection layer isincreased and irradiation with ions is performed under the samecondition to form the fragile layer, the thickness of a semiconductorlayer which is separated from the semiconductor substrate andtransferred to the supporting substrate can be decreased. For example,although it depends on the ratio of ion species (H⁺ ions, H₂ ⁺ ions, andH₃ ⁺ ions), in the case where the fragile layer is formed under theabove-described condition, if a silicon oxynitride film (with athickness of 50 nm) and a silicon nitride oxide film (with a thicknessof 50 nm) are stacked as a protection layer over the semiconductorsubstrate, the thickness of the semiconductor layer which is transferredto the supporting substrate is approximately 120 nm; whereas, if asilicon oxynitride film (with a thickness of 100 nm) and a siliconnitride oxide film (with a thickness of 50 nm) are stacked as aprotection layer over the semiconductor substrate, the thickness of thesemiconductor layer which is transferred to the supporting substrate isapproximately 70 nm.

When helium (He) or hydrogen is used as a source gas, irradiation isperformed with an accelerating voltage in the range of 10 to 200 kV andwith a dose in the range of 1×10¹⁶ to 6×10¹⁶ ions/cm² so that thefragile layer can be formed. When helium is used as a source gas,irradiation can be performed with He⁺ ions as the main ions without massseparation. Further, if hydrogen is used as a source gas, irradiationcan be performed with H₃ ⁺ ions or H₂ ⁺ ions as the main ions. Ionspecies change depending on a plasma generation method, pressure, thesupply of a source gas, and an accelerating voltage.

As an example of formation of the fragile layer, a silicon oxynitridefilm (with a thickness of 50 nm), a silicon nitride oxide film (with athickness of 50 nm), and a silicon oxide film (with a thickness of 50nm) are stacked as a protection layer over the semiconductor substrate,and irradiation with hydrogen is performed at an acceleration voltage of40 kV and a dose of 2×10¹⁶ ions/cm² to form the fragile layer in thesemiconductor substrate. Then, a silicon oxide film (with a thickness of50 nm) is formed as an insulating layer over the silicon oxide film,which is the top layer of the protection layer. As another example offormation of the fragile layer, a silicon oxide film (with a thicknessof 100 nm) and a silicon nitride oxide film (with a thickness of 50 nm)are stacked as a protection layer over the semiconductor substrate, andirradiation with hydrogen is performed at an acceleration voltage of 40kV and a dose of 2×10¹⁶ ions/cm² to form the fragile layer in thesemiconductor substrate. Then, a silicon oxide film (with a thickness of50 nm) is formed as an insulating layer over the silicon nitride oxidefilm, which is the top layer of the protection layer. Note that thesilicon oxynitride film and the silicon nitride oxide film may be formedby a plasma CVD method, and the silicon oxide film may be formed by aCVD method using an organic silane gas.

When a glass substrate which is used in the electronics industry, suchas an aluminosilicate glass substrate, an aluminoborosilicate glasssubstrate, or a barium borosilicate glass substrate is employed as thesupporting substrate 101, the glass substrate contains a slight amountof alkali metal such as sodium, and this slight amount of impurity mayadversely affect the characteristics of a semiconductor element such asa transistor. The silicon nitride oxide film prevents such metalimpurities contained in the supporting substrate 101 from diffusing fromthe supporting substrate 101 to the semiconductor substrate side. Notethat a silicon nitride film may be formed as an alternative to thesilicon nitride oxide film. A stress relieving layer such as a siliconoxynitride film or a silicon oxide film is preferably provided betweenthe semiconductor substrate and the silicon nitride oxide film. When astacked structure of the silicon nitride oxide film and the siliconoxynitride film is provided, diffusion of impurities to thesemiconductor substrate can be prevented and stress distortion can bereduced.

Next, as shown in FIG. 3B, a silicon oxide film is formed as theinsulating layer 104 over a surface which is to form a bond with thesupporting substrate. As the silicon oxide film, a silicon oxide filmformed by a chemical vapor deposition method using an organic silane gasis preferable. Alternatively, a silicon oxide film formed by a chemicalvapor deposition method using a silane gas can be employed. Filmformation by a chemical vapor deposition method is performed at atemperature, for example, 350° C. or lower (a specific example is 300°C.) at which the fragile layer 110 that is formed in a single-crystalsemiconductor substrate is not degassed. In addition, heat treatmentwhich releases a single-crystal semiconductor layer or a polycrystallinesemiconductor layer from a single-crystal semiconductor substrate or apolycrystalline semiconductor substrate employs a temperature which ishigher than a temperature for the film formation.

The insulating layer 104 has a smooth surface and forms a hydrophilicsurface. A silicon oxide film is suitably used as this insulating layer104. In particular, a silicon oxide film which is formed by a chemicalvapor deposition method using an organic silane gas is preferable.Examples of an organic silane gas that can be used aresilicon-containing compounds, such as tetraethoxysilane (TEOS) (chemicalformula: Si(OC₂H₅)₄), trimethylsilane (TMS: (CH₃)₃SiH),tetramethylsilane (chemical formula: Si(CH₃)₄),tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane(OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC₂H₅)₃), andtrisdimethylaminosilane (SiH(N(CH₃)₂)₃). Note that when the siliconoxide film is formed by a chemical vapor deposition method using organicsilane as a source gas, a gas which provides oxygen is preferably mixed.As a gas which provides oxygen, oxygen, nitrous oxide, nitrogen dioxide,or the like can be used. In addition, an inert gas such as argon,helium, or nitrogen, or a hydrogen gas may be mixed. Alternatively, theinsulating layer 104 can be a silicon oxide film which is formed by achemical vapor deposition method using silane such as monosilane,disilane, or trisilane as a source gas. Also in this case, a gas whichprovides oxygen, an inert gas, or the like is preferably mixed. Filmformation by a chemical vapor deposition method is performed at atemperature, for example, 350° C. or lower at which the fragile layer110 that is formed in the a semiconductor substrate 108 is not degassed.In addition, heat treatment which releases a semiconductor layer from asingle-crystal semiconductor substrate or a polycrystallinesemiconductor substrate employs a temperature which is higher than atemperature for film formation. Note that a chemical vapor depositionmethod includes a plasma CVD method, a thermal CVD method, and aphoto-CVD method.

Further, the insulating layer 104 can be formed using silicon oxidewhich is formed by heat treatment in an oxidizing atmosphere, a siliconoxide which grows by reaction of oxygen radicals, a chemical oxide whichis formed with an oxidizing chemical solution, or the like. Theinsulating layer 104 may be an insulating layer having siloxane(Si—O—Si) bonds. Further, the insulating layer 104 may be formed byreaction between the organic silane gas and oxygen radicals or nitrogenradicals.

The insulating layer 104 which has a smooth surface and forms ahydrophilic surface is formed to have a thickness of 5 to 500 nm,preferably 10 to 200 nm. With this thickness, it is possible to smoothsurface roughness of the insulating layer 104 and also to ensuresmoothness of the insulating layer 104. In addition, distortion of thesemiconductor substrate 108 and the supporting substrate that are bondedto each other can be eased. The surface of the insulating layer 104 ispreferably set as follows: an arithmetic mean roughness Ra is less than0.8 nm and a root-mean-square roughness Rms is less than 0.9 nm; morepreferably, Ra is 0.4 nm or less and Rms is 0.5 nm or less; and stillmore preferably, Ra is 0.3 nm or less and Rms is 0.4 nm or less. Forexample, Ra is 0.27 nm and Rms is 0.34 nm. In this specification, Ra isarithmetic mean roughness, Rms is root-mean-square roughness, and themeasurement area is 2 or 10 μm².

The supporting substrate 101 may be provided with a silicon oxide filmsimilarly to the insulating layer 104. In other words, in bonding thesemiconductor layer 102 to the supporting substrate 101, a strong bondcan be formed when the insulating layer 104 formed of a silicon oxidefilm preferably using organic silane as a material is provided over oneor both surfaces which are bonded to each other.

FIG. 3C illustrates a mode in which the supporting substrate 101 and asurface of the insulating layer 104 over the semiconductor substrate 108are disposed in close contact with each other and bonded to each other.Surfaces that form the bond are sufficiently cleaned. The surfaces ofthe supporting substrate 101 and the insulating layer 104 over thesemiconductor substrate 108 may be cleaned by megasonic cleaning or thelike. Further, the surfaces may be cleaned with ozone water after themegasonic cleaning to remove an organic substance and to improve thehydrophilicity of the surfaces.

By making the supporting substrate 101 and the insulating layer 104 faceeach other and pressing a part thereof from outside, the distancebetween the bonding surfaces is locally reduced, whereby the supportingsubstrate 101 and the insulating layer 104 are attracted each other byincrease in van der Waals forces or contribution of hydrogen bonding.Further, since the distance between the supporting substrate 101 and theinsulating layer 104, which face each other, in an adjacent region isreduced, a region which is strongly influenced by van der Waals forcesor a region to which hydrogen bonding contributes is widened.Accordingly, bonding proceeds and spreads to the entire bondingsurfaces. A pressing pressure may be, for example, approximately 100 to5000 kPa.

In order to form a favorable bond, the surfaces may be activated. Forexample, the surfaces which are to form a bond are irradiated with anatomic beam or an ion beam. In the case of using an atomic beam or anion beam, an inert gas neutral atom beam or inert gas ion beam of argonor the like can be used. Further, plasma irradiation or radicaltreatment is performed. Such a surface treatment facilitates a bondbetween different kinds of materials even at a temperature of 200 to400° C.

Further, in order to improve bonding strength at the bonding interfacebetween the supporting substrate and the insulating layer, heattreatment is preferably performed. For example, heat treatment isperformed in a temperature condition of 70 to 350° C. (e.g., at 200° C.for 2 hours) in an oven, a furnace, or the like.

In FIG. 3D, after the supporting substrate 101 and the semiconductorsubstrate 108 are attached to each other, heat treatment is performed torelease the semiconductor substrate 108 from the supporting substrate101 with the fragile layer 110 serving as a cleavage plane. When theheat treatment is performed at, for example, 400 to 700° C., the volumeof microvoids formed in the fragile layer 110 is changed, which enablescleavage to occur along the fragile layer 110. Since the insulatinglayer 104 is bonded to the supporting substrate 101, the semiconductorlayer 102 having the same crystallinity as the semiconductor substrate108 is left over the supporting substrate 101.

The heat treatment in the temperature range of 400 to 700° C. may besuccessively performed with the same apparatus as the above-describedheat treatment for improving the bonding strength or with a differentapparatus. For example, after heat treatment in a furnace at 200° C. for2 hours, the temperature is increased to around 600° C., held for 2hours, and decreased to be in a range from room temperature to 400° C.,and then the substrates are taken out of the furnace. Alternatively,heat treatment may be performed with a temperature increasing from roomtemperature. Further alternatively, heat treatment may be performed in afurnace at 200° C. for 2 hours, and then, in a temperature range of 600to 700° C. with a rapid thermal annealing (RTA) apparatus for 1 to 30minutes (e.g., at 600° C. for 7 minutes or at 650° C. for 7 minutes).

By the heat treatment in the temperature range of 400 to 700° C.,bonding between the insulating layer and the supporting substrate shiftsfrom hydrogen bonding to covalent bonding, and the element which hasbeen added to the fragile layer is taken out and the pressure rises,whereby the semiconductor layer can be released from the semiconductorsubstrate. After the heat treatment, the supporting substrate and thesemiconductor substrate are in a state where one of them is located overthe other, and the supporting substrate and the semiconductor substratecan be separated from each other without large force. For example, onesubstrate located over the other substrate is lifted with a vacuumchuck, so that the supporting substrate and the semiconductor substratecan be easily separated. At this time, if the lower substrate isfastened with a vacuum chuck or a mechanical chuck, the supportingsubstrate and the semiconductor substrate can be separated from eachother without horizontal deviation.

Note that although an example in which the semiconductor substrate 108is smaller than the supporting substrate 101 is shown in FIGS. 3A to 3Cand FIGS. 4A to 4D, the present invention is not limited thereto. Thesemiconductor substrate 108 and the supporting substrate 101 may be thesame size or the semiconductor substrate 108 may be larger than thesupporting substrate 101.

FIGS. 4A to 4D illustrate steps of forming a semiconductor layer usingan insulating layer which is bonded to the semiconductor layer and whichis provided over the supporting substrate. FIG. 4A shows a step in whichthe semiconductor substrate 108, which is provided with a silicon oxidefilm serving as the protection layer 121, is irradiated with ions thatare accelerated by an electric field so as to reach a given depth toform the fragile layer 110. Ion irradiation is performed similarly tothe case of FIG. 3A. Formation of the protection layer 121 over thesurface of the semiconductor substrate 108 can prevent the surface frombeing damaged and from losing the planarity due to ion irradiation.Further, the protection layer 121 has an effect of preventing diffusionof impurities into the semiconductor layer 102 which is formed using thesemiconductor substrate 108.

FIG. 4B shows a step in which the supporting substrate 101, over whichthe blocking layer 109 and the insulating layer 104 are formed, and asurface of the protective layer 121, which is formed over thesemiconductor substrate 108, are disposed to be in close contact witheach other and bonded. The insulating layer 104 over the supportingsubstrate 101 is disposed in close contact with the protection layer 121of the semiconductor substrate 108 so that they are bonded to eachother.

After that, the semiconductor substrate 108 is released as illustratedin FIG. 4C. Heat treatment for releasing the semiconductor layer isperformed similarly to the case of FIG. 3D. The heat treatment inbonding and separating steps is performed at a temperature equal to orlower than the temperature at which heat treatment is performed on thesupporting substrate 101 in advance. Thus, the semiconductor substrateillustrated in FIG. 4C can be obtained.

As the supporting substrate 101, a substrate having an insulatingproperty or a substrate having an insulating surface can be used, and itis possible to employ any of a variety of glass substrates that are usedin the electronics industry and referred to as non-alkali glasssubstrates, such as an aluminosilicate glass substrate, analuminoborosilicate glass substrate, or a barium borosilicate glasssubstrate. Further, a quartz substrate, a ceramic substrate, a sapphiresubstrate, a metal substrate whose surface is coated with an insulatinglayer, or the like can be used.

Through the above-described process, as illustrated in FIG. 4C, theinsulating layer 104 is formed over the supporting substrate 101 havingan insulating surface and the semiconductor layer 102, which isseparated from the semiconductor substrate 108, is provided over thesupporting substrate 101.

The semiconductor layer 102 provided over the supporting substrate 101is etched into an island shape. A mask 117 is formed over thesemiconductor layer 102. A semiconductor layer 119 having an islandshape is formed by etching the semiconductor layer 102 using the mask117 (see FIG. 4D). While FIGS. 4A to 4D illustrate an example in whichthe protection layer and the insulating layer below the semiconductorlayer are not etched in the etching treatment for forming thesemiconductor layer 119, the protection layer and the insulating layermay also be etched in the etching treatment for forming thesemiconductor layer 119. In this case, the protection layer and theinsulating layer reflect the shape of the semiconductor layer 119 havingan island shape and provided only under the semiconductor layer 119.

The semiconductor layer which is separated from the semiconductorsubstrate and is transferred to the supporting substrate may havecrystal defects due to the separation step and the ion irradiation step,and may lose surface planarity and have projections and depressions.When a transistor is formed as a semiconductor element using thesemiconductor layer, it is difficult to form a thin gate insulatinglayer with high withstand voltage on the surface of the semiconductorlayer with such projections and depressions. In addition, if thesemiconductor layer has a crystal defect, performance and reliability ofthe transistor are adversely affected; for example, a local interfacestate density with the gate insulating layer is increased.

Therefore, the semiconductor layer is preferably irradiated with anelectromagnetic wave such as laser light to reduce crystal defects.Irradiation with an electromagnetic wave can melt the semiconductorlayer at least partially and can reduce crystal defects in thesemiconductor layer. Note that an oxide film (a natural oxide film or achemical oxide film) formed on the surface of the semiconductor layermay be removed with dilute hydrofluoric acid before irradiation with anelectromagnetic wave.

Any electromagnetic wave may be used as long as it can supply highenergy to the semiconductor layer, and laser light can be preferablyused.

The energy supply to the semiconductor layer can be mainly performed byheat conduction by collision of particles having high energy with thesemiconductor layer by irradiation or the like. As a heat source forproviding particles having high energy, plasma such as normal-pressureplasma, high-pressure plasma, or a thermal plasma jet, or flame of a gasburner or the like can be used. Alternatively, an electron beam or thelike can be used as a heat source.

A wavelength of an electromagnetic wave is set so that it is absorbed bythe semiconductor layer. The wavelength can be determined inconsideration of the skin depth and the like of the electromagneticwave. For example, the wavelength of the electromagnetic wave can be 190to 600 nm. Further, electromagnetic wave energy can be determined inconsideration of the wavelength of the electromagnetic wave, the skindepth of the electromagnetic wave, the thickness of the semiconductorlayer to be irradiated, or the like.

A laser emitting the laser light can be a continuous wave laser, aquasi-continuous wave laser, or a pulsed laser. A pulsed laser ispreferable for partial melting. For example, a gas laser such as anexcimer laser such as a KrF laser, an Ar laser, a Kr laser, or the likecan be used. Alternatively, as a solid state laser, a YAG laser, a YVO₄laser, a YLF laser, a YAlO₃ laser, a GdVO₄ laser, a KGW laser, a KYWlaser, an Alexandrite laser, a Ti:sapphire laser, a Y₂O₃ laser, or thelike can be used. While an excimer laser is a pulsed laser, some solidlasers such as a YAG laser can also be used as a continuous laser, aquasi-continuous laser, and a pulsed laser. Note that in a solid statelaser, any of the second harmonic to the fifth harmonic of a fundamentalwave is preferably used. In addition, a semiconductor laser such as GaN,GaAs, GaAlAs, InGaAsP, or the like can be used.

As long as the semiconductor layer can be irradiated withelectromagnetic wave energy, lamp light may be used. For example, lightemitted from an ultraviolet lamp, a black light, a halogen lamp, a metalhalide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodiumlamp, or a high pressure mercury lamp may be used. Flash annealing usingthe above-mentioned lamp light may be used. Since flash annealing whichis performed by preferably using a halogen lamp, a xenon lamp, or thelike takes a very short treatment time, increase in temperature of thesupporting substrate can be suppressed.

A shutter; a reflector such as a mirror or a half mirror; an opticalsystem including a cylindrical lens, a convex lens, or the like may beprovided to adjust the shape or path of the electromagnetic wave.

Note that as for an irradiation method with the electromagnetic wave,the semiconductor layer can be selectively irradiated with theelectromagnetic wave or the semiconductor layer can be irradiated withlight (the electromagnetic wave) by scanning the light (theelectromagnetic wave) in the XY axes directions. In this case, a polygonmirror or a galvanometer mirror is preferably used for the opticalsystem.

Irradiation with the electromagnetic wave can be performed in anatmosphere which contains oxygen, such as an air atmosphere or in aninert atmosphere such as a nitrogen atmosphere. To perform irradiationwith the electromagnetic wave in an inert atmosphere, irradiation withthe electromagnetic wave may be performed in an airtight chamber, andthe atmosphere in this chamber may be controlled. In the case where achamber is not used, a nitrogen atmosphere can be formed by spraying aninert gas such as a nitrogen gas or the like on a surface irradiatedwith the electromagnetic wave.

Further, polishing treatment may be performed on the surface of thesemiconductor layer to which high energy is supplied by electromagneticwave irradiation or the like to reduce crystal defects of the surface.Polishing treatment can enhance the planarity of the surface of thesemiconductor layer.

For the polishing treatment, a chemical mechanical polishing (CMP)method or a liquid jet polishing method can be used. Note that thesurface of the semiconductor layer is cleaned and purified before thepolishing treatment. The cleaning may be megasonic cleaning, two-fluidjet cleaning, or the like and dust or the like on the surface of thesemiconductor layer is removed by cleaning. In addition, it ispreferable to remove a natural oxide film or the like on the surface ofthe semiconductor layer to expose the semiconductor layer by usingdilute hydrofluoric acid.

In addition, the surface of the semiconductor layer may be subjected topolishing treatment (or etching treatment) before the electromagneticwave irradiation.

In this embodiment mode, when a single-crystal silicon substrate is usedas the semiconductor substrate 108, a single-crystal silicon layer canbe obtained as the semiconductor layer 119. Further, since a method formanufacturing an SOI substrate of a semiconductor device in thisembodiment mode allows a process temperature to be 700° C. or lower, aglass substrate can be employed as the supporting substrate 101. Thatis, similarly to a conventional thin film transistor, the transistor inthis embodiment mode can be formed over a glass substrate and asingle-crystal silicon layer can be employed as the semiconductor layer.Accordingly, a transistor with high performance and high reliabilitywhich can, for example, operate at high speed and low driving voltageand have a low subthreshold swing and high electron field-effectmobility can be manufactured over a supporting substrate such as a glasssubstrate.

Next, a method for manufacturing the semiconductor device illustrated inFIG. 1A which employs the SOI substrate manufactured as described aboveis described with reference to FIGS. 7A to 7F and FIGS. 8A to 8D.

In FIG. 7A, the blocking layer 109, the insulating layer 104, theprotection layer 121, and the semiconductor layer 119 are formed overthe supporting substrate 101. The semiconductor layer 119, the blockinglayer 109, the insulating layer 104, and the protection layer 121correspond to those in FIGS. 4A to 4D. Note that while an example whichemploys the SOI substrate having the structure illustrated in FIG. 7A isgiven here, the SOI substrate having another structure described in thisspecification can be employed.

In the semiconductor layer 119, a p-type impurity such as boron,aluminum, or gallium or an n-type impurity such as phosphorus or arsenicis preferably added to a region where an n-channel field-effecttransistor or a p-channel field-effect transistor is to be formed. Inother words, a p-type impurity is added to a region where an n-channelfield-effect transistor is to be formed and an n-type impurity is addedto a region where a p-channel field-effect transistor is to be formed,so that so-called well regions are formed. The dose of impurity ions maybe approximately 1×10¹² to 1×10¹⁴ ions/cm². Further, in the case ofadjusting the threshold voltage of the field-effect transistor, a p-typeor n-type impurity may be added to the well regions.

The semiconductor layer 119 may be further etched to have island shapesin accordance with arrangement of the semiconductor elements.

An oxide film over the semiconductor layer is removed and a gateinsulating layer 205 is formed to cover the semiconductor layer 119.

The gate insulating layer 205 may be formed using silicon oxide, or maybe formed with a stacked-layer structure of silicon oxide and siliconnitride. The gate insulating layer 205 may be formed by depositing aninsulating film by a plasma CVD method or a low-pressure CVD method.Alternatively, the gate insulating layer 205 may be formed bysolid-phase oxidation or solid-phase nitridation with plasma treatmentbecause a gate insulating layer which is formed by oxidizing ornitriding a semiconductor layer by plasma treatment is dense, has highwithstand voltage, and is highly reliable.

Further, as the gate insulating layer 205, a high dielectric constantmaterial such as zirconium dioxide, hafnium oxide, titanium dioxide, ortantalum pentoxide may be used. When a high dielectric constant materialis used for the gate insulating layer 205, gate leak current can bereduced.

The gate electrode layer 206 is formed over the gate insulating layer205 (see FIG. 7B). The gate electrode layer 206 can be formed by asputtering method, an evaporation method, a CVD method, or the like. Thegate electrode layer 206 may be formed using an element selected fromtantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum(Al), copper (Cu), chromium (Cr), or neodymium (Nd), or an alloymaterial or compound material containing any of those elements as itsmain component. Further, as the gate electrode layer 206, asemiconductor film typified by a polycrystalline silicon film doped withan impurity element such as phosphorus can be used, or an AgPdCu alloymay be used.

The impurity regions 208 a and 208 b, which are n-type impurity regions,are formed by adding an impurity element 207 imparting n-typeconductivity using the gate electrode layer 206 as a mask. In thisembodiment mode, phosphine (PH₃) is used as a doping gas containing animpurity element. Here, doping is performed such that the impurityregions 208 a and 208 b contain the impurity element imparting n-typeconductivity at a concentration of approximately 5×10¹⁹ to 5×10²⁰atoms/cm³. In addition, the channel formation region 209 is formed inthe semiconductor layer 119 (see FIG. 7C).

The impurity regions 208 a and 208 b are n-type high-concentrationimpurity regions and serve as a source and a drain.

Heat treatment, intense light irradiation, or laser light irradiationmay be performed to activate the impurity element, which can repairplasma damage of the gate insulating layer and of the interface betweenthe gate insulating layer and the semiconductor layer as well asactivation.

Subsequently, an interlayer insulating layer which covers the gateelectrode layer and the gate insulating layer is formed. In thisembodiment mode, the interlayer insulating layer is a stacked layer ofthe insulating layer 210 which contains hydrogen and serves as aprotection film and the planarization layer 211 (see FIG. 7D).

Further, heat treatment is performed in a nitrogen atmosphere at 300 to550° C. for 1 to 12 hours to hydrogenate the semiconductor layer.Preferably, this heat treatment is performed at 400 to 500° C. This stepterminates dangling bonds of the semiconductor layer with hydrogen whichis contained in the insulating layer 210, which is the interlayerinsulating layer. In this embodiment mode, the heat treatment isperformed at 410° C. for one hour.

In the present invention, the planarization layer 211 is formed torelieve projections and depressions on the surface which are generatedby the semiconductor layer, the gate electrode layer, and the like andto planarize the surface. Accordingly, the planarization layer 211 isformed to have a thickness with which the surface thereof is planarized.Note that the surface may be planarized by chemical mechanical polishing(CMP).

The insulating layer 210 and the planarization layer 211 may be asilicon nitride film, a silicon nitride oxide film, a silicon oxynitridefilm, or a silicon oxide film which are formed by a sputtering method orplasma CVD. Alternatively, a single layer or a stacked layer of three ormore layers which includes another insulating film containing siliconmay be used.

The insulating layer 210 and the planarization layer 211 can be formedof a material selected from aluminum nitride (AlN), aluminum oxynitride(AlON), aluminum nitride oxide (AlNO) containing more nitrogen thanoxygen, aluminum oxide, diamond-like carbon (DLC), nitrogen-containingcarbon (CN), or another inorganic insulating substance. Further, asiloxane resin may be used. Note that a siloxane resin refers to a resinincluding an Si—O—Si bond. Siloxane has a skeleton formed by a bond ofsilicon (Si) and oxygen (O), in which an organic group containing atleast hydrogen (such as an alkyl group or aromatic hydrocarbon) is usedas a substituent. The organic group may include a fluoro group.

Alternatively, an organic insulating material which can withstandsubsequent heat treatment may be used. As such an organic material,polyimide, acrylic, polyamide, polyimide amide, resist,benzocyclobutene, or polysilazane can be given. A coated film which isformed by a coating method and has favorable planarity may be used asthe planarization layer 211.

Dip coating, spray coating, a doctor knife, a roll coater, a curtaincoater, a knife coater, a CVD method, an evaporation method, or the likecan be used for forming the insulating layer 210 and the planarizationlayer 211. The insulating layer 210 and the planarization layer 211 maybe formed by a droplet discharge method. If a droplet discharge methodis used, a material liquid can be saved. In addition, a method capableof transferring or drawing a pattern like a droplet discharge method,for example, a printing method (a method for forming a pattern, such asscreen printing or offset printing) can be used.

The insulating layer 212 is formed over the planarization layer 211 asan insulating layer which is bonded to a second semiconductor layer. Thematerial and forming step of the insulating layer 212 may be similar tothose for the insulating layer 104. The insulating layer 212 can be asmooth layer (an arithmetic mean roughness Ra is less than 0.3 nm (ameasurement area 10 μm²)) and a silicon oxide film or a siliconoxynitride film, a laminate of a silicon nitride film and a siliconoxide film stacked in that order over the planarization layer 211, or alaminate of a silicon oxynitride film and a silicon oxide film stackedin that order over the planarization layer 211. The insulating layer 212is preferably formed by a PECVD method at a low temperature of 350° C.or lower. For example, in this embodiment mode, a silicon oxide film isformed as the insulating layer 212, using tetraethoxysilane as anorganic silane gas by a chemical vapor deposition method. A siliconnitride film or silicon oxynitride film prevents impurities fromdiffusing from the planarization layer 211 through the insulating layer212 to a semiconductor layer 215 and the gate insulating layer 217 whichare formed thereover.

The semiconductor layer 215 is bonded to the insulating layer 212 to beformed over the planarization layer 211 in a similar manner in which thesemiconductor layer 102 is bonded to the insulating layer 104 and isseparated from the semiconductor substrate 108 (see FIG. 7E). Thesemiconductor layer 215 is separated from the semiconductor substrate213 in which a fragile layer 214 is formed and is bonded to theinsulating layer 212 with heat treatment.

The semiconductor layer 215 may be irradiated with laser light to reducecrystal defects. Further, the surface of the semiconductor layer 215 maybe subjected to polishing treatment. Polishing treatment can enhance theplanarity of the surface of the semiconductor layer 215.

Note that in this embodiment mode, a single-crystal semiconductorsubstrate with a {100} crystal plane orientation is selected as thesemiconductor substrate 108, which is a first semiconductor substrate,while a single-crystal semiconductor substrate with a {110} crystalplane orientation is selected as the semiconductor substrate 213, whichis a second semiconductor substrate. Note that a combination of thecrystal plane orientation of the first semiconductor substrate and thecrystal plane orientation of the second semiconductor substrate is notlimited to the combination in this embodiment mode. For example, asubstrate with a {110} crystal plane orientation may be used as thefirst semiconductor substrate, and a substrate with a {100} crystalplane orientation may be used as the second semiconductor substrate. Inthat case, it is preferable that a p-channel field-effect transistor bemanufactured using the first semiconductor substrate and an n-channelfield-effect transistor be manufactured using the second semiconductorsubstrate.

Then, the semiconductor layer 215, which is a thin film, is selectivelyetched to form the semiconductor layer 216 having an island shape overthe insulating layer 212 (see FIG. 7F).

The gate insulating layer 217 and the gate electrode layer 218 areformed over the semiconductor layer 216 (see FIG. 8A).

The impurity regions 220 a and 220 b, which are p-type impurity regions,are formed by adding an impurity element 219 imparting p-typeconductivity using the gate electrode layer 218 as a mask. Doping isperformed such that the impurity regions 220 a and 220 b contain theimpurity element imparting p-type conductivity at a concentration ofapproximately 1×10²⁰ to 5×10²¹ atoms/cm³. In addition, the channelformation region 221 is formed in the semiconductor layer 216 (see FIG.8B). The impurity regions 220 a and 220 b are p-type high-concentrationimpurity regions and serve as a source and a drain.

Subsequently, an interlayer insulating layer which covers the gateelectrode layer and the gate insulating layer is formed. In thisembodiment mode, the interlayer insulating layer is a stacked layer ofthe insulating layer 222 which contains hydrogen and serves as aprotection film and the planarization layer 223.

Further, heat treatment is performed in a nitrogen atmosphere at 300 to550° C. for 1 to 12 hours to hydrogenate the semiconductor layer.Preferably, this heat treatment is performed at 400 to 500° C. This stepterminates dangling bonds of the semiconductor layer with hydrogen whichis contained in the insulating layer 222, which is the interlayerinsulating layer. In this embodiment mode, the heat treatment isperformed at 410° C. for one hour. This heat treatment may also serve asthe heat treatment for the semiconductor layer 119 and the insulatinglayer 210.

In the present invention, the planarization layer 223 is formed torelieve projections and depressions on the surface which are generatedby the semiconductor layer, the gate electrode layer, and the like andto planarize the surface. Accordingly, the planarization layer 223 isformed to have a thickness with which the surface thereof is planarized.Note that the surface may be planarized by chemical mechanical polishing(CMP).

The gate insulating layer 217, the gate electrode layer 218, theinsulating layer 222, and the planarization layer 223 correspond to thegate insulating layer 205, the gate electrode layer 206, the insulatinglayer 210, and the planarization layer 211, respectively, and they canbe formed of similar materials and by similar steps.

Then, contact holes (openings) which reach the semiconductor layer 119are formed in the gate insulating layer 205, the insulating layer 210,the planarization layer 211, the insulating layer 212, the gateinsulating layer 217, the insulating layer 222, and the planarizationlayer 223 using a mask formed of a resist; and contact holes (openings)which reach the semiconductor layer 216 are formed in the gateinsulating layer 217, the insulating layer 222, and the planarizationlayer 223 using a mask formed of a resist. Etching may be performed onceor plural times in accordance with a selectivity of a material which isused. The gate insulating layer 205, the insulating layer 210, theplanarization layer 211, the insulating layer 212, the gate insulatinglayer 217, the insulating layer 222, and the planarization layer 223 areselectively removed by etching to form openings which reach the impurityregions 208 a and 208 b or the impurity regions 220 a and 220 b, whichare source regions and drain regions.

A method and a condition of the etching may be set as appropriatedepending on the materials of the gate insulating layer 205, theinsulating layer 210, the planarization layer 211, the insulating layer212, the gate insulating layer 217, the insulating layer 222, and theplanarization layer 223 in which the contact holes are formed. Wetetching, dry etching, or both of them can be used as appropriate. Inthis embodiment mode, dry etching is used. As an etching gas, achlorine-based gas typified by Cl₂, BCl₃, SiCl₄ or CCl₄; afluorine-based gas typified by CF₄, SF₆, or NF₃; or O₂ can be used asappropriate. Further, an inert gas may be added to an etching gas to beused. As an inert element to be added, one or a plurality of elementsselected from He, Ne, Ar, Kr, or Xe can be used.

As an etchant of wet etching, a hydrofluoric acid-based solution such asa mixed solution of ammonium hydrogen fluoride and ammonium fluoride maybe used.

A conductive film is formed to cover the openings, and the conductivefilm is etched to form the wiring layers 224, 225, and 226. The wiringlayers 224, 225, and 226 are electrically connected to portions ofsource regions and drain regions and serve as source electrode layersand drain electrode layers. The wiring layers can be formed by forming aconductive film by a PVD method, a CVD method, an evaporation method, orthe like, and then etching the conductive film into a desired shape.Alternatively, the conductive layers can be selectively formed inpredetermined positions by a droplet discharge method, a printingmethod, an electroplating method, or the like. Further, a reflow methodor a damascene method may be used. The wiring layers are formed of ametal such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe,Ti, Zr, or Ba; or Si or Ge; or an alloy or nitride thereof. Further, alaminate of those layers may be employed.

In this embodiment mode, the wiring layers 240 a and 240 b are formed asembedded wiring layers to fill contact holes formed in the gateinsulating layer 217, the insulating layer 222, and the planarizationlayer 223; and the wiring layers 240 c and 240 d are formed as embeddedwiring layers to fill contact holes formed in the gate insulating layer205, the insulating layer 210, the planarization layer 211, theinsulating layer 212, the gate insulating layer 217, the insulatinglayer 222, and the planarization layer 223 (see FIG. 8C). The wiringlayers 240 a, 240 b, 240 c, and 240 d, which are the embedded wiringlayers, are formed by forming a conductive film having an enoughthickness to fill the contact holes and polishing the conductive film bya CMP method or the like so that the conductive film can remain only incontact hole portions and an unnecessary part of the conductive film areremoved.

The wiring layers 241 a, 241 b, and 241 c are formed as lead wiringlayers over the wiring layers 240 a, 240 b, 240 c, and 240 d, which arethe embedded wiring layer, whereby the wiring layers 224, 225, and 226are formed.

Through the above-described steps, a semiconductor device having a CMOSstructure, including the field-effect transistor 230, which is ann-channel field-effect transistor and the field-effect transistor 231,which is a p-channel field-effect transistor can be manufactured (seeFIG. 8D). Note that the field-effect transistor 230 and the field-effecttransistor 231 are electrically connected by the wiring layer 225.

The field-effect transistor 230 is bonded to the insulating layer 104and is provided over the supporting substrate 101, while thefield-effect transistor 231 is bonded to the insulating layer 212 whichis formed over the planarization layer 211 covering the field-effecttransistor 230 and is provided over the planarization layer 211. Thefield-effect transistor 230 and the field-effect transistor 231 arestacked.

According to the present invention, high performance semiconductorelements can be stacked; therefore, higher integration of thesemiconductor devices can be achieved.

In addition, in attaching the semiconductor layers to the supportingsubstrate, the semiconductor layers are formed over different planarinsulating layers; therefore, the insulating layers and thesemiconductor layers can be easily bonded to each other.

As in this embodiment mode, when field-effect transistors of differentconductivity types are formed over different insulating layers,parasitic capacitance between the semiconductor layers of thefield-effect transistors of different conductivity types and parasiticcapacitance between the gate electrode layers of the field-effecttransistors of different conductivity types can be reduced. Accordingly,a high-performance semiconductor device can be manufactured.

The field-effect transistor is not limited to the one described in thisembodiment mode, and may have a single gate structure, in which onechannel formation region is formed, a double gate structure, in whichtwo channel formation regions are formed, or a triple gate structure, inwhich three channel formation regions are formed.

In addition, while this embodiment mode describes a CMOS structure inwhich the field-effect transistors which are stacked have differentconductivity types, field-effect transistors of the same conductivitytype may be stacked.

As described above, in this embodiment mode, semiconductor devicesincluding more highly integrated and higher performance semiconductorelements can be manufactured.

Embodiment Mode 2

This embodiment mode describes an example in which steps of separating asemiconductor layer from the semiconductor substrate and bonding thesemiconductor layer to a supporting substrate are different from stepsin Embodiment Mode 1. Repetitive description of the same portion or aportion having a similar function to the portions in Embodiment Mode 1is omitted.

In this embodiment mode, when a semiconductor layer is transferred froma semiconductor substrate, the semiconductor substrate is selectivelyetched (this step is also referred to as groove processing) and aplurality of semiconductor layers which are divided to have the size ofsemiconductor elements to be manufactured are transferred to asupporting substrate. Thus, a plurality of island-shaped semiconductorlayers can be formed over the supporting substrate. The semiconductorlayers which are processed into an element size in advance aretransferred; therefore, the semiconductor layers can be transferred tothe supporting substrate in units of the semiconductor layers.Therefore, the size and shape of the semiconductor substrate are notlimited. Accordingly, the semiconductor layers can be more efficientlytransferred to a large-sized supporting substrate.

The semiconductor layer which is thus formed over the supportingsubstrate may be etched so that the shape is processed, modified, andcontrolled precisely. Accordingly, error in a formation position and adefect in the shape of the semiconductor layer due to patternmisalignment caused by light or the like in light exposure for forming aresist mask going around the resist mask, positional misalignment causedby a bonding step in transferring the semiconductor layer, or the likecan be modified.

Accordingly, a plurality of semiconductor layers having a desired shapecan be formed over the supporting substrate with a high yield.Therefore, a semiconductor device which includes high performancesemiconductor elements and an integrated circuit which are more precisecan be manufactured over a large-sized substrate with high throughputand high productivity.

FIG. 5A illustrates a state in which a protection layer 154 and asilicon nitride film 152 are formed over a semiconductor substrate 158.The silicon nitride film 152 is used as a hard mask in performing grooveprocessing on the semiconductor substrate 158. The silicon nitride film152 may be formed by depositing silane and ammonia by a vapor depositionmethod.

Then, ion irradiation is performed to form a fragile layer 150 in thesemiconductor substrate 158 (see FIG. 5B). Ion irradiation is performedin consideration of the thickness of a semiconductor layer which is tobe transferred to a supporting substrate. In consideration of thethickness, an accelerating voltage for irradiating the semiconductorsubstrate 158 with ions is set so that a deep part of the semiconductorsubstrate 158 is irradiated. With this treatment, the fragile layer 150is formed in a region at a certain depth from the surface of thesemiconductor substrate 158.

The groove processing is performed in consideration of the shape ofsemiconductor layers of semiconductor elements. That is, in order totransfer a semiconductor layer of a semiconductor element to thesupporting substrate, the groove processing is performed on thesemiconductor substrate 158 such that a portion which is transferred asa semiconductor layer remains as a convex portion.

A mask 153 is formed of photoresist. The silicon nitride film 152 andthe protection layer 154 are etched using the mask 153 to form aprotection layer 162 and a silicon nitride layer 163 (see FIG. 5C).

Then, the semiconductor substrate 158 is etched using the siliconnitride layer 163 as a hard mask to form the semiconductor substrate 158having a fragile layer 165 and a semiconductor layer 166 (see FIG. 5D).In the present invention, a semiconductor region which is part of asemiconductor substrate which is processed into a convex shape using afragile layer and by groove processing is referred to as thesemiconductor layer 166 as in FIG. 5D.

The depth of etching the semiconductor substrate 158 is set asappropriate in consideration of the thickness of the semiconductor layerwhich is transferred to the supporting substrate. The thickness of thesemiconductor layer can be set by a depth where hydrogen ions reach byirradiation. The groove formed in the semiconductor substrate 158 ispreferably deeper than the fragile layer. In this groove processing, ifthe groove is processed to be deeper than the fragile layer, the fragilelayer can be left only in a region of the semiconductor layer which isto be released.

The silicon nitride layer 163 on the surface is removed (see FIG. 5E).Then, the surface of the protection layer 162 of the semiconductorsubstrate 158 and the supporting substrate 151 are bonded to each other(see FIG. 6A).

The surface of the supporting substrate 151 is provided with a blockinglayer 159 and an insulating layer 157. The blocking layer 159 isprovided so as to prevent impurities such as sodium ions from diffusingfrom the supporting substrate 151 and contaminating the semiconductorlayer. Note that in a case where there is no possibility of diffusion ofimpurities from the supporting substrate 151 which causes adverseeffects on the semiconductor layer, the blocking layer 159 can beomitted. The insulating layer 157 is provided to form a bond with theprotection layer 162.

The bond can be formed by disposing the protection layer 162 of thesemiconductor substrate 158 and the insulating layer 157 of thesupporting substrate, the surfaces of which are cleaned, in closecontact with each other. The bond can be formed at room temperature.This bonding is performed at the atomic level, and a strong bond isformed at room temperature by van der Waals forces. Since grooveprocessing has been performed on the semiconductor substrate 158, aconvex portion forming the semiconductor layer is in contact with thesupporting substrate 151.

After the bond between the semiconductor substrate 158 and thesupporting substrate 151 is formed, heat treatment is performed torelease a semiconductor layer 164 from the semiconductor substrate 158and to fasten the semiconductor layer 164 to the supporting substrate151, as illustrated in FIG. 6B. The volume of microvoids formed in thefragile layer 150 is changed and a crack is generated along the fragilelayer 150, whereby the semiconductor layer is released. After that, inorder to further strengthen the bond, heat treatment is preferablyperformed. As described above, the semiconductor layer is formed overthe insulating surface. FIG. 6B illustrates a state in which thesemiconductor layer 164 is bonded to the supporting substrate 151.

In this embodiment mode, since the semiconductor layers which areprocessed into an element size in advance are transferred, transfer tothe supporting substrate can be performed in units of the semiconductorlayers; therefore, the size and shape of the semiconductor substrate arenot limited. Accordingly, semiconductor layers having various shapes canbe formed over the semiconductor substrate. For example, the shapes ofthe semiconductor layers can be freely formed in accordance with a maskof a light-exposure apparatus which is used for etching, a stepper ofthe light-exposure apparatus for forming a mask pattern, and a panel orchip size of a semiconductor device which is cut from a large-sizedsubstrate.

The semiconductor layer 164 may be used as it is as a semiconductorlayer of a semiconductor element, or may be etched to process the shape.

FIGS. 6C and 6D illustrate an example in which the semiconductor layer164 which is transferred is further etched to have the shape processed.A mask 167 is formed to expose a periphery of the semiconductor layer164, which is an unnecessary part.

The semiconductor layer 164 is etched using the mask 167 to form asemiconductor layer 169. In this embodiment mode, the protection layer162 under the semiconductor layer is etched together with thesemiconductor layer to be a protection layer 168 (see FIG. 6D). Asdescribed above, when the shape of the semiconductor layer is furtherprocessed after the semiconductor layer is transferred to the supportingsubstrate, misalignment of a region where the semiconductor layer isformed, defects in shape, or the like which occur in the manufacturingprocess can be modified.

FIGS. 5A to 5E and FIGS. 6A to 6D illustrate an example in which asemiconductor layer is transferred to an insulating layer over thesupporting substrate. Needless to say, this embodiment mode can beemployed for forming a semiconductor layer over an insulating layerwhich is over a planarization layer, as a semiconductor layer for asemiconductor element which is in the upper layer.

This embodiment mode can be implemented in combination with EmbodimentMode 1 as appropriate.

Embodiment Mode 3

This embodiment mode describes an example in which steps of separating asemiconductor layer from the semiconductor substrate and bonding thesemiconductor layer to a supporting substrate are different from stepsin Embodiment Mode 1. Repetitive description of the same portion or aportion having a similar function to the portions in Embodiment Mode 1is omitted.

This embodiment mode describes an example in which after a semiconductorlayer is separated from a semiconductor substrate, the semiconductorlayer is bonded to a supporting substrate.

As described in Embodiment Mode 2 with reference to FIGS. 5A to 5E, thefragile layer is formed in the semiconductor substrate and a groove isformed. Groove processing is performed in consideration of the shape ofa semiconductor layer of a semiconductor element. That is, in order totransfer the semiconductor layer of the semiconductor element to thesupporting substrate, the groove processing is performed on asemiconductor substrate 301 such that a portion which is transferred asthe semiconductor layer remains as a convex portion. In FIG. 15A, thesemiconductor substrate 301, a fragile layer 302, a semiconductor layer308 which is part of the semiconductor substrate 301, and an insulatingfilm 304 are formed. In this embodiment mode, silicon oxide is used forthe insulating film 304.

Then, heat treatment is performed and neighboring minute voids in thefragile layer 302 are coupled and the volume of the minute voids isincreased. As a result, the semiconductor substrate 301 is cleaved alongthe fragile layer 302; thus, the semiconductor layer 308 is releasedwith the insulating film 304 from the semiconductor substrate 301. Theheat treatment may be performed in a temperature range of 400 to 600° C.

Note that heat treatment may be performed using dielectric heating witha high frequency wave such as a microwave. The heat treatment usingdielectric heating can be performed by irradiating the semiconductorsubstrate 301 with a high-frequency wave with a frequency of 300 MHz to3 THz which is produced with a high-frequency generator. Specifically,for example, irradiation is performed with a microwave of 2.45 GHz at900 W for 14 minutes to couple the neighboring minute voids in thefragile layer; thus, the semiconductor substrate 301 is finally cleaved.

Then, as shown in FIG. 15B, a collet 305 is fixed to the insulating film304 formed over the semiconductor layer 308, and the semiconductor layer308 is pulled apart from the semiconductor substrate 301. Even ifcleavage of the semiconductor substrate 301 by the above-described heattreatment is incomplete, the semiconductor layer 308 is completelyreleased from the semiconductor substrate 301 and a semiconductor layer303 can be obtained by applying force to the collet 305. The collet 305can be a means that can be selectively fixed to one of the semiconductorlayers 308, such as a chuck like a vacuum chuck or a mechanical chuck, amicroneedle with an adhesive attached to a tip, or the like. FIG. 15Billustrates a case where a vacuum chuck is used as the collet 305.

As the adhesive which is attached to the microneedle, an epoxy-basedadhesive, a ceramic-based adhesive, a silicone-based adhesive, a lowtemperature coagulant, or the like can be used. As the low temperaturecoagulant, for example, MW-1 (manufactured by Eminent SupplyCorporation) can be used. MW-1 has a freezing point of 17° C. and has anadhesive effect at a temperature of 17° C. or lower (preferably at 10°C. or lower) and does not have an adhesive effect at a temperature of17° C. or higher (preferably approximately 25° C.).

Note that hydrogenation may be performed on the semiconductor substrate301 before the cleavage of the semiconductor substrate 301.Hydrogenation is performed, for example, at 350° C. in a hydrogenatmosphere for approximately two hours.

Next, as shown in FIG. 15C, the semiconductor layer 303 and a supportingsubstrate 310 are attached to each other so that a surface exposed byreleasing the semiconductor layer 303 faces the supporting substrate310. In this embodiment mode, because an insulating film 311 is formedover the supporting substrate 310, the semiconductor layer 303 and thesupporting substrate 310 can be attached to each other by bonding theinsulating film 311 and the semiconductor layer 303. After bonding thesemiconductor layer 303 and the insulating film 311, heat treatment at400 to 600° C. is preferably performed in order to further strengthenthe bond.

The bond is formed by van der Waals forces; therefore, a strong bond canbe formed even at room temperature. Note that since the above-describedbonding can be performed at a low temperature, various substrates can beused as the supporting substrate 310. For example, as the supportingsubstrate 310, a substrate such as a quartz substrate or a sapphiresubstrate can be used as well as a glass substrate made ofaluminosilicate glass, barium borosilicate glass, aluminoborosilicateglass, or the like. Further, as the supporting substrate 310, asemiconductor substrate formed of silicon, gallium arsenide, indiumphosphide, or the like can be used. Alternatively, a metal substratesuch as a stainless steel substrate may be used as the supportingsubstrate 310.

Note that the supporting substrate 310 does not necessarily have theinsulating film 311 on its surface. In the case where the insulatingfilm 311 is not formed, the supporting substrate 310 and thesemiconductor layer 303 can be bonded to each other. Note that byformation of the insulating film 311 on the surface of the supportingsubstrate 310, impurities such as an alkali metal or an alkaline-earthmetal can be prevented from entering the semiconductor layer 303 fromthe supporting substrate 310.

If the insulating film 311 is formed, not the supporting substrate 310but the insulating film 311 is bonded to the semiconductor layer 303;therefore, kinds of substrates which can be used as the supportingsubstrate 310 are further increased. A substrate formed from a flexiblesynthetic resin such as plastic generally tends to have a low uppertemperature limit, but can be used as the supporting substrate 310 inthe case where the insulating film 311 is formed, as long as thesubstrate can withstand processing temperatures of the manufacturingprocess.

Note that before or after the semiconductor layer 303 is attached to thesupporting substrate 310, thermal annealing using irradiation with laserlight may be performed on a surface exposed by release of thesemiconductor layer 303. If thermal annealing is performed before thesemiconductor layer 303 is attached to the supporting substrate 310, thesurface exposed by release is planarized and bonding strength can befurther increased. If thermal annealing is performed after thesemiconductor layer 303 is attached to the supporting substrate 310,part of the semiconductor layer 303 is melted and bonding strength canbe further increased.

Note that the semiconductor layer 303 may be attached to the supportingsubstrate 310 not only by the bond but also by application of highfrequency oscillation of approximately 10 MHz to 1 THz to thesemiconductor layer 303, which generates frictional heat between thesemiconductor layer 303 and the supporting substrate 310 to melt part ofthe semiconductor layer 303 with the heat, whereby the semiconductorlayer 303 is attached to the supporting substrate 310.

Note that when MW-1 is used as a low temperature coagulant, first, thelow temperature coagulant which is attached to the tip of a microneedleis made in contact with the insulating film 304 at a temperature (e.g.,approximately 25° C.) at which the low temperature coagulant does nothave an adhesive effect. Next, a temperature is lowered to a temperature(e.g., approximately 5° C.) at which the low temperature coagulant hasan adhesive effect and the low temperature coagulant is solidified,whereby the microneedle and the insulating film 304 are fixed. After thesemiconductor layer 303 pulled apart from the semiconductor substrate301 is attached to the supporting substrate 310, the temperature of thelow temperature coagulant is raised to a temperature (e.g.,approximately 25° C.) at which the low temperature coagulant does nothave an adhesive effect again, whereby the microneedle can be pulledapart from the semiconductor layer 303.

The insulating film 304 over the semiconductor layer 303 is removed, andthe semiconductor layer 303 having an island shape is formed over thesupporting substrate 310 and the insulating film 311 (see FIG. 15D). Thesemiconductor layer 303 may be further etched to have the shapeprocessed.

When the surface of the semiconductor layer which is exposed by thecleavage faces the supporting substrate as illustrated in FIGS. 15A to15D, a surface with higher planarity is in contact with a gateinsulating film; therefore, the interface state density between thesemiconductor layer and the gate insulating film can be low and uniform.Accordingly, polishing for planarizing the surface of the semiconductorlayer which comes into contact with the gate insulating film can beomitted, or a polishing time can be shortened, whereby cost can besuppressed and throughput can be improved.

Note that the semiconductor layer can be attached to the supportingsubstrate so that the surface of the semiconductor layer exposed by thecleavage comes into contact with the gate insulating film. This exampleis described with reference to FIGS. 16A to 16D and FIGS. 17A to 17C.

In FIG. 16A, a semiconductor substrate 321, a fragile layer 322, asemiconductor layer 328 which is part of the semiconductor substrate,and an insulating film 324 are formed as in FIG. 15A. In this embodimentmode, silicon oxide is used for the insulating film 324.

Next, as shown in FIG. 16B, the semiconductor substrate 321 is fixed toa holding means 325. The semiconductor substrate 321 is fixed so thatthe semiconductor layer 328 faces the holding means 325. The holdingmeans 325 can be a large-sized vacuum chuck or mechanical chuck whichcan withstand heat treatment in a later step and be fixed so as to beoverlapped with a plurality of semiconductor layers (in FIGS. 16A to16D, the semiconductor layer 328). In specific, the holding means 325can be a porous vacuum chuck, a noncontact vacuum chuck, or the like.This embodiment mode describes an example in which a vacuum chuck isused as the holding means 325.

Then, heat treatment is performed and neighboring minute voids in thefragile layer 322 are coupled and the volume of the minute voids isincreased. As a result, the semiconductor substrate 321 is cleaved alongthe fragile layer 322 as illustrated in FIG. 16C; thus, thesemiconductor layer 328, which has been part of the semiconductorsubstrate 321, becomes the semiconductor layer 323 and is released withthe insulating film 324 from the semiconductor substrate 321. The heattreatment may be performed in a temperature range of 400 to 600° C.

Note that heat treatment may be performed using dielectric heating witha high frequency wave such as a microwave.

Note that hydrogenation may be performed on the semiconductor substrate321 before the cleavage of the semiconductor substrate 321.

Then, as shown in FIG. 16D and FIG. 17A, a collet 327 is fixed to thesurface of the semiconductor layer 323 which is exposed by the cleavage,and the semiconductor layer 323 is pulled apart from the holding means325. The collet 327 can be a means that can be selectively fixed to thesemiconductor layer 323, such as a chuck like a vacuum chuck or amechanical chuck, a microneedle with an adhesive attached to a tip, orthe like. FIG. 16D and FIG. 17A illustrate a case where a vacuum chuckis used as the collet 327.

Although this embodiment mode describes an example in which the collet327 is fixed to the surface of the semiconductor layer 323 which isexposed by the cleavage, a protection film such as an insulating filmmay be formed in order to prevent the semiconductor layer 323 from beingdamaged by the collet 327. Note that the protection film is removedafter the semiconductor layer 323 is attached to the supportingsubstrate 330 in a later step.

As the adhesive which is attached to the microneedle, an epoxy-basedadhesive, a ceramic-based adhesive, a silicone-based adhesive, a lowtemperature coagulant, or the like can be used.

Next, as shown in FIG. 17B, the semiconductor layer 323 and thesupporting substrate 330 are attached to each other so that theinsulating film 324 faces the supporting substrate 330, in other words,a surface opposite to the surface exposed by the cleavage faces thesupporting substrate 330. In this embodiment mode, because an insulatingfilm 331 is formed over the supporting substrate 330, the semiconductorlayer 323 and the supporting substrate 330 can be attached to each otherby bonding the insulating film 324 and the insulating film 331 (see FIG.17C). After bonding the insulating film 331 and the insulating film 324,heat treatment at 400 to 600° C. is preferably performed in order tofurther strengthen the bond.

The bond is formed by van der Waals forces, so that a strong bond can beformed even at room temperature. Note that since the above-describedbonding can be performed at a low temperature, various substrates can beused as the supporting substrate 330.

Note that the supporting substrate 330 does not necessarily have theinsulating film 331 on its surface.

Note that there are a case where the semiconductor substrate is warpedor deformed and a case where an end portion of the semiconductorsubstrate is slightly rounded. Further, when the semiconductor substrateis irradiated with hydrogen or a noble gas, or hydrogen ions or noblegas ions to release a semiconductor layer from the semiconductorsubstrate, there is a case where irradiation with the above-mentionedgas or ions is not sufficiently performed on the end portion of thesemiconductor substrate. Therefore, it is difficult to release a portionof the semiconductor layer which is at an end portion of thesemiconductor substrate, and in the case where the semiconductorsubstrate is attached to a supporting substrate, and then is separatedto form the semiconductor layer by cleavage of the semiconductorsubstrate, the distance between the semiconductor layers may be severalmillimeter to several centimeters. However, in this embodiment mode, thesemiconductor substrate is cleaved to form the semiconductor layerbefore the semiconductor substrate is attached to the supportingsubstrate. Thus, when the semiconductor layers are attached to thesupporting substrate, the distance between the semiconductor layers canbe suppressed as small as about several tens of micrometers, and it iseasy to form a semiconductor device using adjacent semiconductor layers.

In a method for manufacturing a semiconductor device of this embodimentmode, since a plurality of semiconductor layers can be attached to onesupporting substrate using a plurality of semiconductor substrates,processing can be performed with high throughput. In addition, a crystalplane orientation of the semiconductor layer can be selected asappropriate in accordance with the polarity of a semiconductor element;therefore, the mobility of the semiconductor element can be increasedand a semiconductor device that can operate at higher speed can beprovided.

In addition, a plurality of semiconductor layers can be formed bycleavage at plural portions of a semiconductor substrate and theplurality of semiconductor layers can be attached to a supportingsubstrate. Therefore, positions to which the plurality of semiconductorlayers are attached can be selected in accordance with polarity andlayout of semiconductor elements in a semiconductor device.

This embodiment mode can be implemented in combination with EmbodimentMode 1 as appropriate.

Embodiment Mode 4

This embodiment mode describes a structure of a manufacturing apparatusof a semiconductor device which can be applied to the present invention(in particular, to Embodiment Mode 3).

FIG. 18A illustrates an example of a structure of a manufacturingapparatus which can be applied to the present invention (in particular,to Embodiment Mode 3). The manufacturing apparatus shown in FIG. 18Aincludes a stage 902 over which a semiconductor substrate 901 is placedand a stage 904 over which a supporting substrate 903 is placed. Notethat while FIG. 18A illustrates an example in which the semiconductorsubstrate 901 and the supporting substrate 903 are placed over differentstages, the present invention is not limited to this structure. Thesemiconductor substrate 901 and the supporting substrate 903 can beplaced over one stage.

Further, while FIG. 18A illustrates one stage 902 over which onesemiconductor substrate 901 is placed, the present invention is notlimited to this structure. For example, a manufacturing apparatus whichcan be applied to the present invention may have a plurality of stages902 over which one semiconductor substrate 901 is placed. Alternatively,a plurality of the semiconductor substrates 901 may be placed over thestage 902.

The manufacturing apparatus illustrated in FIG. 18A has a collet 905which is fixed to a semiconductor layer formed by cleavage of thesemiconductor substrate 901 and attaches the semiconductor layer to apredetermined position of the supporting substrate 903. The collet 905can be a means that can be selectively fixed to one of the semiconductorlayers, such as a chuck like a vacuum chuck or a mechanical chuck, amicroneedle with an adhesive attached to its tip, or the like.

In addition, the manufacturing apparatus illustrated in FIG. 18A has atleast a collet driving portion 906 that controls the position of thecollet 905, a stage driving portion 907 that controls positions of thestage 902 and the stage 904, and a CPU 908 which controls operations ofthe collet driving portion 906 and the stage driving portion 907 inaccordance with positional information of the collet or positionalinformation of the stage.

The positional information of the collet or the positional informationof the stage can be obtained based on positional information where asemiconductor layer is in the semiconductor substrate 901 and where thesemiconductor layer is to be attached to the supporting substrate 903.Note that the manufacturing apparatus illustrated in FIG. 18A may beprovided with a camera having an imaging device such as a charge coupleddevice (CCD) in order to position the semiconductor substrate 901 or thesupporting substrate 903.

When a heat sink for absorbing and dissipating heat of the semiconductorsubstrate 901 is provided over the stage 902 and a microneedle whose tipis provided with a low temperature coagulant is provided as the collet905, the temperature of the semiconductor substrate 901 can be loweredefficiently by the heat sink.

Further, a manufacturing apparatus which can be applied to the presentinvention may have a reversing device for picking up a semiconductorlayer from the semiconductor substrate 901 and then turning over thesemiconductor layer. FIG. 18B illustrates a mode in which a reversingdevice 909 is added to the manufacturing apparatus in FIG. 18A. Thereversing device 909 has a reversing collet 910 and can pick up asemiconductor layer and hold it temporarily with the reversing collet910. The collet 905 can receive the semiconductor layer from thereversing collet 910 by being fixed to a surface of the semiconductorlayer which is opposite from the surface fixed to the reversing collet910.

Next, in order to illustrate a positional relationship and specificstructures of the semiconductor substrate 901, the stage 902, thesupporting substrate 903, the stage 904, the collet 905, the colletdriving portion 906, and the stage driving portion 907 in FIG. 18A, aperspective view of them is illustrated in FIG. 19. Note that FIG. 19illustrates an example which employs a stage driving portion 907 a whichcontrols the operation of the stage 902 and a stage driving portion 907b which controls the operation of the stage 904.

In accordance with instructions from the CPU 908, the stage drivingportion 907 a moves the stage 902 in the X direction or the Y directionintersecting the X direction. Note that the stage driving portion 907 amay move the stage 902 in the Z direction as well as the X direction orthe Y direction. The Z direction exists on a plane different from theplane formed by the X direction and the Y direction. Similarly, thestage driving portion 907 b moves the stage 904 in the X direction orthe Y direction intersecting the X direction. The stage driving portion907 b may move the stage 904 in the Z direction as well as the Xdirection or the Y direction. The Z direction exists on a planedifferent from the plane formed by the X direction and the Y direction.

The collet 905 picks up one of a plurality of semiconductor layersformed by cleavage of the semiconductor substrate 901. Then, the colletdriving portion 906 transfers the collet 905 from the semiconductorsubstrate 901 to the supporting substrate 903, while the collet 905holds the semiconductor layer. Note that although FIG. 19 illustrates anexample in which one collet 905 comes and goes between the semiconductorsubstrate 901 and the supporting substrate 903, a plurality of collets905 may be employed. When the plurality of collets 905 are employed, aplurality of collet driving portions 906 for independently controllingthe operation of each collet 905 may be prepared, or all the collets 905may be controlled with one collet driving portion 906.

Next, FIG. 20 illustrates a mode in which the plurality of stages 902are employed in FIG. 19. FIG. 20 illustrates an example in which a stage902 a, a stage 902 b, and a stage 902 c are employed, and all of thestage 902 a, the stage 902 b, and the stage 902 c are controlled by thestage driving portion 907 a. Note that a plurality of stage drivingportions 907 a may be prepared in order to independently control theoperation of the stage 902 a, the stage 902 b, and the stage 902 c.

FIG. 20 illustrates a state in which a semiconductor substrate 901 a, asemiconductor substrate 901 b, and a semiconductor substrate 901 c areplaced over the stage 902 a, the stage 902 b, and the stage 902 c,respectively. The crystal plane orientations of the semiconductorsubstrate 901 a, the semiconductor substrate 901 b, and thesemiconductor substrate 901 c may be the same or different.

In FIG. 20, the collet 905 picks up one of a plurality of semiconductorlayers formed by cleavage of the semiconductor substrate 901 a, thesemiconductor substrate 901 b, and the semiconductor substrate 901 c.The collet driving portion 906 transfers the collet 905 from thesemiconductor substrate 901 a, the semiconductor substrate 901 b, or thesemiconductor substrate 901 c to the supporting substrate 903 while thecollet 905 holds the semiconductor layer. Note that although FIG. 20illustrates an example in which one collet 905 comes and goes betweenthe semiconductor substrate 901 a, the semiconductor substrate 901 b,and the semiconductor substrate 901 c, and the supporting substrate 903;a plurality of collets 905 may be employed so that at least one collet905 is employed for each of the semiconductor substrate 901 a, thesemiconductor substrate 901 b, and the semiconductor substrate 901 c.

The manufacturing apparatus which can be applied to the presentinvention can transfer and attach a plurality of semiconductor layersformed by one semiconductor substrate 901 to desired positions over thesupporting substrate 903 as appropriate.

This embodiment can be implemented in combination with Embodiment Mode 3as appropriate.

Embodiment Mode 5

This embodiment mode describes a structure in which a semiconductorlayer suitable for an n-channel field-effect transistor and asemiconductor layer suitable for a p-channel field-effect transistor aretaken out from a semiconductor substrate.

As described in Embodiment Modes 1 to 4, since a semiconductor layerwhich is separated and transferred from a semiconductor substrate isused for a semiconductor device according to the present invention, acrystal plane orientation of the semiconductor layer can be selected byselecting an appropriate semiconductor substrate. Therefore, asemiconductor layer having a crystal plane orientation which is mostsuitable for the conductivity type of a field-effect transistor can beselected for each of an n-channel field-effect transistor and ap-channel field-effect transistor.

In the case of bonding semiconductor layers having different crystalplane orientation to a supporting substrate, crystal axes of channellength directions of the semiconductor layers are set in certaindirections. Carrier mobility of electrons and holes flowing through asemiconductor layer of a field-effect transistor can be increased bymatching anisotropy in crystal plane orientation of the semiconductorlayer and anisotropy in a channel length direction along which carriersflow. This is because effective mass of carriers has anisotropy incrystals.

For example, in the case of taking a semiconductor layer for ann-channel field-effect transistor from a semiconductor substrate with a{100} crystal plane orientation, it is preferable that a channel lengthdirection be a <100> axis. If there are a plurality of <100> crystalaxes in a semiconductor layer surface, any of the crystal axes can beset along a channel length direction.

On the other hand, in order to form a semiconductor layer for ap-channel field-effect transistor, it is preferable that a semiconductorsubstrate with a {110} crystal plane orientation be used and a channellength direction be parallel to a <110> axis. In such a manner, when a<100> axis is employed for an n-channel field-effect transistor and a<110> axis is employed for a p-channel field-effect transistor, mobilityof electrons and holes flowing through a channel formation region can befurther increased.

This embodiment can be implemented in combination with any of EmbodimentModes 1 to 4 as appropriate.

Embodiment Mode 6

This embodiment mode describes a structure in which a semiconductorlayer suitable for an n-channel field-effect transistor and asemiconductor layer suitable for a p-channel field-effect transistor aretaken out from a semiconductor substrate with a single crystal plane.

A case of using a semiconductor substrate with a {110} crystal planeorientation is described. In this case, the semiconductor layer of ann-channel field-effect transistor is formed to have a <100> axis as achannel length direction. On the other hand, the semiconductor layer ofa p-channel field-effect transistor is formed to have a <110> axis as achannel length direction.

According to this embodiment mode, a first semiconductor layer in ann-channel field-effect transistor and a second semiconductor layer in ap-channel field-effect transistor can be taken out from a semiconductorsubstrate having a single crystal plane and provided over a supportingsubstrate, and a semiconductor integrated circuit or the like whichincludes different crystal axes in channel length directions can beobtained. When a <100> axis is employed for an n-channel field-effecttransistor and a <110> axis is employed for a p-channel field-effecttransistor, mobility of electrons and holes flowing through a channelformation region can be further increased.

Since a semiconductor layer of an n-channel field-effect transistor anda semiconductor layer of a p-channel field-effect transistor areindependently bonded to a supporting substrate, design flexibility in acircuit configuration of the n-channel field-effect transistor and thep-channel field-effect transistor is ensured; accordingly, theintegration density of the semiconductor integrated circuit or the likecan be increased. Because a semiconductor device employing asemiconductor integrated circuit of the present invention hasfield-effect transistors with high mobility over a supporting substrate,high-speed operation, low-voltage driving, and lower power consumptioncan be achieved. Further, according to this embodiment mode, a structurefor element isolation is not necessary; therefore, a manufacturingprocess can be simplified.

This embodiment can be implemented in combination with any of EmbodimentModes 1 to 4 as appropriate.

Embodiment Mode 7

This embodiment mode describes an example of a semiconductor device withhigh performance and high reliability. Specifically, as an example ofthe semiconductor device, examples of a microprocessor and asemiconductor device which has an arithmetic function and can transmitand receive data without contact are described.

FIG. 9 illustrates an example of a microprocessor 500 as an example of asemiconductor device. The microprocessor 500 is manufactured using thesemiconductor substrate according to the above embodiment modes. Thismicroprocessor 500 has an arithmetic logic unit (also referred to as anALU) 501, an ALU controller 502, an instruction decoder 503, aninterrupt controller 504, a timing controller 505, a register 506, aregister controller 507, a bus interface (Bus I/F) 508, a read onlymemory (ROM) 509, and a memory interface (ROM I/F) 510.

An instruction input to the microprocessor 500 via the bus interface 508is input to the instruction decoder 503 and decoded, and then input tothe ALU controller 502, the interrupt controller 504, the registercontroller 507, and the timing controller 505. The ALU controller 502,the interrupt controller 504, the register controller 507, and thetiming controller 505 perform various control based on the decodedinstruction. Specifically, the ALU controller 502 generates a signal forcontrolling operation of the arithmetic logic unit 501. The interruptcontroller 504 judges an interrupt request from an external input/outputdevice or a peripheral circuit based on its priority or a mask state,and processes the request while a program is executed in themicroprocessor 500. The register controller 507 generates an address ofthe register 506, and reads and writes data from and to the register 506in accordance with the state of the microprocessor 500. The timingcontroller 505 generates signals for controlling timing of operation ofthe arithmetic logic unit 501, the ALU controller 502, the instructiondecoder 503, the interrupt controller 504, and the register controller507. For example, the timing controller 505 is provided with an internalclock generator for generating an internal clock signal CLK2 based on areference clock signal CLK1, and supplies the clock signal CLK2 to eachof the above-mentioned circuits. Note that FIG. 9 illustrates a mereexample of the simplified structure of the microprocessor 500, andpractical microprocessors can be provided with various structuresdepending on the usage.

Since the microprocessor 500 has an integrated circuit which employssemiconductor layers with a certain crystal orientation which are bondedto a glass substrate, lower power consumption can be achieved as well ashigher processing speed.

Next, an example of a semiconductor device provided with an arithmeticfunction by which data can be transmitted and received without contactis described with reference to FIG. 10. FIG. 10 illustrates an exampleof a computer which operates to transmit and receive signals to and froman external device by wireless communication (such a computer ishereinafter referred to as an “RFCPU”). An RFCPU 511 has an analogcircuit portion 512 and a digital circuit portion 513. The analogcircuit portion 512 includes a resonance circuit 514 having a resonantcapacitor, a rectifier circuit 515, a constant voltage circuit 516, areset circuit 517, an oscillator circuit 518, a demodulation circuit519, a modulation circuit 520, and a power supply control circuit 530.The digital circuit portion 513 includes an RF interface 521, a controlregister 522, a clock controller 523, a CPU interface 524, a centralprocessing unit 525, a random access memory 526, and a read only memory527.

The operation of the RFCPU 511 having such a structure is brieflydescribed below. The resonance circuit 514 generates an inducedelectromotive force based on a signal received by an antenna 528. Theinduced electromotive force is stored in a capacitor portion 529 via therectifier circuit 515. The capacitor portion 529 is preferably formedusing a capacitor such as a ceramic capacitor or an electric doublelayer capacitor. The capacitor portion 529 is not necessarily integratedwith the RFCPU 511 and may be attached as another component to asubstrate having an insulating surface which is included in the RFCPU511.

The reset circuit 517 generates a signal that resets and initializes thedigital circuit portion 513. For example, the reset circuit 517generates a signal that rises after increase in power supply voltage asa reset signal. The oscillator circuit 518 changes the frequency and theduty ratio of a clock signal depending on a control signal generated bythe constant voltage circuit 516. The demodulation circuit 519 having alow pass filter, for example, binaries amplitude fluctuation ofreception signals of an amplitude shift keying (ASK) system. Themodulation circuit 520 transmits transmission data by changing theamplitude of transmission signals of an amplitude shift keying (ASK)system. The modulation circuit 520 changes the amplitude of transmissionsignals of an amplitude shift keying (ASK) system to transmit thetransmission signals. The modulation circuit 520 changes the resonancepoint of the resonance circuit 514, thereby changing the amplitude ofcommunication signals. The clock controller 523 generates a controlsignal for changing the frequency and the duty ratio of the clock signaldepending on the power supply voltage or current consumption in thecentral processing unit 525. The power supply voltage is monitored bythe power supply control circuit 530.

A signal that is input to the RFCPU 511 from the antenna 528 isdemodulated by the demodulation circuit 519, and then divided into acontrol command, data, and the like by the RF interface 521. The controlcommand is stored in the control register 522. The control commandincludes reading of data stored in the read only memory 527, writing ofdata to the random access memory 526, an arithmetic instruction to thecentral processing unit 525, and the like. The central processing unit525 accesses the read only memory 527, the random access memory 526, andthe control register 522 via the CPU interface 524. The CPU interface524 has a function of generating an access signal for any of the readonly memory 527, the random access memory 526, and the control register522, based on an address requested by the central processing unit 525.

As an arithmetic method of the central processing unit 525, a method canbe employed, in which the read only memory 527 stores an operatingsystem (OS) and a program is read and executed at the time of startingoperation. Note that a method can be employed, in which a circuitdedicated to arithmetic is formed and an arithmetic process is conductedusing hardware. In a method in which both hardware and software areused, a method can be employed, in which part of process is conducted inthe circuit dedicated to arithmetic and the other part of the arithmeticprocess is conducted by the central processing unit 525 using a program.

Since an integrated circuit is formed using semiconductor layers each ofwhich has a certain crystal plane orientation and which are bonded to aglass substrate in the RFCPU 511, higher processing speed and lowerpower consumption can be achieved. Accordingly, even when the capacitorportion 529 which supplies electric power is downsized, operation for along period of time can be ensured.

Embodiment Mode 8

This embodiment mode describes an example of a mounting structure of asemiconductor device according to the present invention.

An integrated circuit according to the present invention can be formedby highly integrating semiconductor elements in three dimensions. Insuch a highly integrated circuit, it is preferable to mount a heat sinkthat efficiently dissipates heat generated by the integrated circuit.

FIG. 22A illustrates a mode in which an integrated circuit is mounted ona printed circuit board as an example of a semiconductor deviceaccording to the present invention.

In FIG. 22A, integrated circuit packages 601 a, 601 b, and 601 c in eachof which an integrated circuit is packaged in an insulating chassiswhich are mounted on a printed circuit board 603 are provided in contactwith a heat sink 600 via heat dissipation sheets 602 a, 602 b, and 602 cwhich further improve a heat dissipation effect. The heat sink 600 isprovided so as to cover the integrated circuit packages 601 a, 601 b,and 601 c, and is electrically connected to the printed circuit board603 via conductive metal layers 604 a and 604 b, and interceptselectromagnetic waves emitted from the integrated circuit packages 601a, 601 b, and 601 c. FIG. 22A illustrates a structure in which the heatsink which covers the integrated circuits can dissipate heat from theintegrated circuits and can intercept electromagnetic waves to preventelectromagnetic interference.

FIG. 22B illustrates an example in which a heat dissipation sheet and aheat sink are directly mounted on integrated circuits. In FIG. 22B,integrated circuits 611 a and 611 b are provided in contact with a heatsink 610 via heat dissipation sheets 612 a and 612 b, and are packagedby the heat sink 610 and a chassis 613 that adheres the heat sink 610using adhesive layers 614 a and 614 b.

In this manner, when the heat sink is mounted, a semiconductor devicewith higher reliability and higher performance can be made by efficientheat dissipation and cooling.

This embodiment can be implemented in combination with any of theforegoing embodiment modes as appropriate.

Embodiment Mode 9

This embodiment mode describes an example of a usage mode of asemiconductor device described in the foregoing embodiment modes.Specifically, an application example of a semiconductor device capableof inputting and outputting data without contact is described withreference to the drawings. The semiconductor device to and from whichdata can be input and output without contact is also referred to as anRFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag,an electronic tag, or a wireless chip depending on the uses.

An example of a top view structure of a semiconductor device of thisembodiment mode is described with reference to FIG. 12. A semiconductordevice 2180 illustrated in FIG. 12 includes a thin film integratedcircuit 2131 including a plurality of elements such as transistors forforming a memory portion and a logic portion, and a conductive layer2132 which serves as an antenna. The conductive layer 2132 which servesas an antenna is electrically connected to the thin film integratedcircuit 2131. The field-effect transistor according to the presentinvention which is described in Embodiment Modes 1 to 3 can be appliedto the thin film integrated circuit 2131.

FIGS. 13A and 13B are schematic views of a cross section of FIG. 12. Theconductive layer 2132 which serves as an antenna may be provided abovethe elements for forming the memory portion and the logic portion; forexample, the conductive layer 2132 which serves as an antenna can beprovided above CMOS structures 2140 and 2141 which can be manufacturedas a field-effect transistor in the above embodiment modes, with aninsulating layer 2130 interposed therebetween (see FIG. 13A).Alternatively, the conductive layer 2132 which serves as an antenna maybe provided by providing the conductive layer 2132 over a substrate 2133and then attaching the substrate 2133 and the thin film integratedcircuit 2131 each other so as to sandwich the conductive layer 2132 (seeFIG. 13B). FIG. 13B illustrates an example in which a conductive layer2136 provided over the insulating layer 2130 and the conductive layer2132 which serves as an antenna are electrically connected to each otherwith conducting particles 2134 contained in an adhesive resin 2135.

Since a semiconductor device of the present invention has a structure inwhich semiconductor elements are stacked three dimensionally and arehighly integrated, the semiconductor elements can be aligned side byside and in contact with one insulating layer or they can be stackedabove and below with a planarization layer interposed therebetween andbe in contact with different insulating layers. Therefore, arrangementflexibility of semiconductor elements in the semiconductor device isincreased, which can lead to further integration and higher performance.As a semiconductor element, not to mention a field-effect transistor, amemory element which uses a semiconductor layer can be employed;accordingly, a semiconductor device which can satisfy functions requiredfor various applications can be manufactured and provided.

Transistors included in the CMOS structures 2140, 2141, 2142, and 2143have a sidewall insulating layer having a sidewall structure and includelow concentration impurity regions between a channel formation regionand a source region and a drain region, which are high concentrationimpurity regions, in a semiconductor layer. As an example, the CMOSstructures 2140 and 2141 are formed of a field-effect transistor in thelower layer and a field-effect transistor in the upper layer which arestacked, while the CMOS structures 2142 and 2143 are formed offield-effect transistors that are in contact with one insulating layerand arranged in series, and the CMOS structure 2142 and the CMOSstructure 2143 are stacked.

Note that although this embodiment mode describes an example in whichthe conductive layer 2132 which serves as an antenna has a coil shapeand either an electromagnetic induction method or an electromagneticcoupling method is employed, a semiconductor device of the presentinvention is not limited thereto, and a microwave method may beemployed. In the case of a microwave method, the shape of the conductivelayer 2132 which serves as an antenna may be decided as appropriatedepending on the wavelength of an electromagnetic wave which is used.

For example, when a microwave method (e.g., with an UHF band (in therange of 860 MHz to 960 MHz), a frequency band of 2.45 GHz, or the like)is employed as a signal transmission method of the semiconductor device2180, the shape such as the length of the conductive layer which servesas an antenna may be set as appropriate in consideration of thewavelength of an electromagnetic wave which is used in transmitting asignal. For example, the conductive layer which serves as an antenna canbe formed into a linear shape (e.g., a dipole antenna) or a flat shape(e.g., a patch antenna or an antenna having a ribbon shape). Further,the shape of the conductive layer 2132 that serves as an antenna is notlimited to a straight line, the conductive layer 2132 may be a curvedline, in an S-shape, or in a shape combining them may be provided inconsideration of the wavelength of the electromagnetic wave.

The conductive layer 2132 which serves as an antenna is formed of aconductive material by a CVD method, a sputtering method, a printingmethod such as screen printing or gravure printing, a droplet dischargemethod, a dispenser method, a plating method, or the like. Theconductive material is any of a metal element selected from aluminum(Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt),nickel (Ni), palladium (Pd), tantalum (Ta), or molybdenum (Mo), or analloy material or a compound material containing any of those element.The conductive layer 2132 has a single layer structure or astacked-layer structure.

For example, in the case where the conductive layer 2132 which serves asan antenna is formed by a screen printing method, the conductive layer2132 can be provided by selectively printing a conductive paste in whichconductive particles with a grain diameter of several nanometers toseveral tens of micrometers are dissolved or dispersed in an organicresin. As the conductive particle, fine particles or dispersivenanoparticles of one or more metals of silver (Ag), gold (Au), copper(Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta),molybdenum (Mo), titanium (Ti), or a silver halide can be used. Inaddition, as the organic resin contained in the conductive paste, one ora plurality of organic resins serving as a binder, a solvent, adispersant, or a coating of the metal particle can be used. Typically,an organic resin such as an epoxy resin and a silicone resin can begiven as examples. Further, in forming the conductive layer, baking maybe preferably performed after the conductive paste is applied. Forexample, in the case of using fine particles (e.g., fine particles witha grain diameter of 1 nm or more and 100 nm or less) containing silveras a main component of the conductive paste, the conductive layer can beformed by baking the conductive paste at a temperature in the range of150 to 300° C. to be hardened. Alternatively, fine particles containingsolder or lead-free solder as its main component may be used. In thatcase, fine particles having a grain size of 20 μm or less are preferablyused. Solder or lead-free solder has advantages such as low cost.

Lower power consumption can be achieved in a semiconductor device towhich the present invention is applied. Therefore, the present inventionis effective in a small semiconductor device capable of inputting andoutputting data without contact.

Embodiment Mode 10

This embodiment mode describes an example of application of theabove-described semiconductor device capable of inputting and outputtingdata without contact, which is formed according to the presentinvention, with reference to the drawings. The semiconductor device toand from which data can be input and output without contact is alsoreferred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag,a wireless tag, an electronic tag, or a wireless chip depending on theuses.

A semiconductor device 800 has a function of communicating data withoutcontact, and includes a high frequency circuit 810, a power supplycircuit 820, a reset circuit 830, a clock generation circuit 840, a datademodulation circuit 850, a data modulation circuit 860, a controlcircuit 870 which controls another circuit, a memory circuit 880, and anantenna 890 (see FIG. 14A). The high frequency circuit 810 receives asignal by the antenna 890 and also outputs a signal from the antenna 890which is received by the data modulating circuit 860. The power supplycircuit 820 generates a power source potential from a received signal.The reset circuit 830 generates a reset signal. The clock generationcircuit 840 generates various clock signals based on a received signalinput from the antenna 890. The data demodulation circuit 850demodulates and outputs a received signal to the control circuit 870.The data demodulation circuit 850 demodulates and outputs a receivedsignal to the control circuit 870. In the control circuit 870, a codeextraction circuit 910, a code judgment circuit 920, a CRC judgmentcircuit 930, and an output unit circuit 940 are included, for example.Note that the code extraction circuit 910 extracts a plurality of codesincluded in instructions transmitted to the control circuit 870. Thecode judgment circuit 920 compares the extracted codes and codescorresponding to a reference to judge the content of the instructions.The CRC judgment circuit 930 detects the presence of transmission errorsand the like based on the judged codes.

Next, an example of operation of the above-described semiconductordevice is described. First, a radio signal is received by the antenna890. The radio signal is transmitted to the power supply circuit 820 viathe high frequency circuit 810, and a high power supply potential(hereinafter referred to as VDD) is generated. The VDD is supplied toeach circuit included in the semiconductor device 800. A signaltransmitted to the data demodulation circuit 850 via the high frequencycircuit 810 is demodulated (hereinafter, such a signal is referred to asa demodulated signal). Further, the demodulated signal and a signalwhich has passed the high frequency circuit 810 and the reset circuit830 or the clock generation circuit 840 are transmitted to the controlcircuit 870. The signal transmitted to the control circuit 870 isanalyzed by the code extraction circuit 910, the code judgment circuit920, the CRC judgment circuit 930, and the like. Then, based on theanalyzed signal, information of the semiconductor device which is storedin the memory circuit 880 is output. The output information of thesemiconductor device is encoded by passing through the output unitcircuit 940. Furthermore, the encoded information of the semiconductordevice 800 passes through the data modulation circuit 860 andtransmitted by the antenna 890 as a radio signal. Note that among aplurality of circuits included in the semiconductor device 800, a lowpower supply potential (hereinafter, referred to as VSS) is common andVSS can be set as GND.

In this manner, data in the semiconductor device 800 can be read bytransmitting a signal to the semiconductor device 800 from acommunication device and by receiving a signal which is transmitted fromthe semiconductor device 800 by the communication device.

The semiconductor device 800 may be a type in which, for supply of apower supply voltage to each circuit, no electric power supply (battery)is installed and a power supply voltage is supplied by use ofelectromagnetic waves; or the semiconductor device 800 may be a type inwhich, for supply of a power supply voltage to each circuit, an electricpower supply (battery) is installed and a power supply voltage issupplied to each circuit by use of electromagnetic waves and a battery.

Next, an example of a usage mode of a semiconductor device capable ofinputting and outputting data without contact is described. Acommunication device 3200 is provided on a side surface of a portableterminal including a display portion 3210, and a semiconductor device3230 is provided on a side surface of an article 3220 (see FIG. 14B).When the communication device 3200 is put close to the semiconductordevice 3230 on the article 3220, information of the article 3220, suchas its raw material, its place of production, inspection results foreach production step, the history of distribution, or an description ofthe article, is displayed on the display portion 3210. Further, while aproduct 3260 is transported by a conveyor belt, the product 3260 can beinspected using a communication device 3240 and a semiconductor device3250 provided on the product 3260 (see FIG. 14C). Thus, by applicationof a semiconductor device to a system, information can be acquiredeasily, and high function and high added value can be realized. Further,since the semiconductor device according to the present invention canrealize lower power consumption and higher integration, a semiconductordevice provided for an article can be downsized.

A semiconductor device according to the present invention has a verywide range of application and can be used in electronic devices invarious fields.

Embodiment Mode 11

According to the present invention, a semiconductor device serving as achip having a processor circuit (hereinafter also referred to as aprocessor chip, a wireless chip, a wireless processor, a wirelessmemory, a wireless tag, or an RFID tag) can be formed. An applicablerange of a semiconductor device according to the present invention iswide, and the semiconductor device can be applied to any product as longas it clarifies information of an object, such as the history thereof,without contact and is useful for production, management, and the like.For example, the semiconductor device can be mounted on bills, coins,securities, certificates, bearer bonds, packing containers, books,recording media, personal belongings, vehicles, food, clothing, healthproducts, livingwares, medicine, electronic appliances, and the like.Examples of them are described with reference to FIGS. 11A to 11G.

Bills and coins are money circulating in the market, and include onevalid in a certain area (cash voucher), memorial coins, and the like.Securities refer to checks, certificates, promissory notes, and the likeand can be provided with a chip 190 having a processor circuit (see FIG.11A). Certificates refer to driver's licenses, certificates ofresidence, and the like and can be provided with a chip 191 having aprocessor circuit (see FIG. 11B). Personal belongings refer to bags,glasses, and the like and can be provided with a chip 197 having aprocessor circuit (see FIG. 11C). Bearer bonds refer to stamps, ricecoupons, various gift certificates, and the like. Packing containersrefer to wrapping paper for food containers, plastic bottles, and thelike and can be provided with a chip 193 having a processor circuit (seeFIG. 11D). Books refer to hardbacks, paperbacks, and the like and can beprovided with a chip 194 having a processor circuit (see FIG. 11E).Recording media refer to DVD software, video tapes, and the like and canbe provided with a chip 195 having a processor circuit (see FIG. 11F).Vehicles refer to wheeled vehicles like bicycles, ships, and the likeand can be provided with a chip 196 having a processor circuit (see FIG.11G). Food products refer to food items, beverages, and the like.Clothing refers to clothes, footwear, and the like. Health productsrefer to medical instruments, health instruments, and the like.Livingwares refer to furniture, lighting equipment, and the like.Medicine refers to medical products, pesticides, and the like.Electronic devices refer to liquid crystal display devices, EL displaydevices, television sets (TV receivers and flat-screen TV receivers),cellular phones, and the like.

The semiconductor device can be provided by being attached to thesurface of goods or being embedded in goods. For example, in the case ofa book, the semiconductor device may be embedded in a piece of paper;and in the case of a package made from an organic resin, thesemiconductor device may be embedded in the organic resin.

In this manner, when the semiconductor device is provided for packagingcontainers, recording media, personal belongings, foods, clothing,livingwares, electronic devices, and the like, the efficiency of aninspection system, a rental shop system, and the like can be improved.In addition, when the semiconductor device is provided for vehicles,forgery and theft thereof can be prevented. Further, when thesemiconductor device is implanted in creatures such as animals,identification of an individual creature can be easily carried out. Forexample, when the semiconductor device provided with a sensor isimplanted in creatures such as livestocks, its health condition such asa current body temperature as well as its birth year, sex, breed, or thelike can be easily managed.

Note that this embodiment can be implemented in combination with any ofEmbodiment Modes 1 to 10 as appropriate.

This application is based on Japanese Patent Application serial no.2007-218478 filed with Japan Patent Office on Aug. 24, 2007, the entirecontents of which are hereby incorporated by reference.

1. A semiconductor device comprising: an insulating substrate; a firstfield-effect transistor over the insulating substrate, the firstfield-effect transistor comprising: a first single-crystallinesemiconductor layer; a first gate insulating layer; and a first gateelectrode layer; a planarization layer over the first field-effecttransistor; and a second field-effect transistor over the planarizationlayer, the second field-effect transistor comprising: a secondsingle-crystalline semiconductor layer; a second gate insulating layer;and a second gate electrode layer.
 2. The semiconductor device accordingto claim 1, wherein a conductivity type of the first field-effecttransistor is an n-type and a conductivity type of the secondfield-effect transistor is a p-type.
 3. The semiconductor deviceaccording to claim 1, wherein a crystal plane orientation of a plane ofthe first single-crystalline semiconductor layer is a {100} plane and acrystal plane orientation of a plane of the second semiconductor layeris a {110} plane.
 4. The semiconductor device according to claim 3,wherein a crystal axis of a channel length direction of the firstsingle-crystalline semiconductor layer is <100> and a crystal axis of achannel length direction of the second single-crystalline semiconductorlayer is <110>.
 5. The semiconductor device according to claim 1,wherein the first single-crystalline semiconductor layer and the secondsingle-crystalline semiconductor layer are overlapped with each otherwith the planarization layer interposed therebetween, and the firstfield-effect transistor and the second field-effect transistor areelectrically connected to each other by a wiring which is formed in anopening which penetrates the second single-crystalline semiconductorlayer, the planarization layer, and the first gate insulating layer andreaches the first single-crystalline semiconductor layer.
 6. Thesemiconductor device according to claim 1, wherein the insulatingsubstrate is a glass substrate.
 7. A semiconductor device comprising: aninsulating substrate; a first insulating layer over the insulatingsubstrate; a first field-effect transistor over the first insulatinglayer, the first field-effect transistor comprising: a firstsingle-crystalline semiconductor layer; a first gate insulating layer;and a first gate electrode layer; a planarization layer over the firstfield-effect transistor; a second insulating layer over theplanarization layer; and a second field-effect transistor over thesecond insulating layer, the second field-effect transistor comprising:a second single-crystalline semiconductor layer; a second gateinsulating layer; and a second gate electrode layer.
 8. Thesemiconductor device according to claim 7, wherein a conductivity typeof the first field-effect transistor is an n-type and a conductivitytype of the second field-effect transistor is a p-type.
 9. Thesemiconductor device according to claim 7, wherein a crystal planeorientation of a plane of the first single-crystalline semiconductorlayer is a {100} plane and a crystal plane orientation of a plane of thesecond semiconductor layer is a {110} plane.
 10. The semiconductordevice according to claim 9, wherein a crystal axis of a channel lengthdirection of the first single-crystalline semiconductor layer is <100>and a crystal axis of a channel length direction of the secondsingle-crystalline semiconductor layer is <110>.
 11. The semiconductordevice according to claim 7, wherein the first single-crystallinesemiconductor layer and the second single-crystalline semiconductorlayer are overlapped with each other with the planarization layerinterposed therebetween, and the first field-effect transistor and thesecond field-effect transistor are electrically connected to each otherby a wiring which is formed in an opening which penetrates the secondsingle-crystalline semiconductor layer, the planarization layer, and thefirst gate insulating layer and reaches the first single-crystallinesemiconductor layer.
 12. The semiconductor device according to claim 7,wherein the insulating substrate is a glass substrate.
 13. Asemiconductor device comprising: an insulating substrate; a firstfield-effect transistor over the insulating substrate, the firstfield-effect transistor comprising: a first single-crystallinesemiconductor layer; a first gate insulating layer; and a first gateelectrode layer; a planarization layer over the first field-effecttransistor; and a second field-effect transistor over the planarizationlayer, the second field-effect transistor comprising: a secondsingle-crystalline semiconductor layer; a second gate insulating layer;and a second gate electrode layer, wherein a crystal plane orientationof the first single-crystalline semiconductor layer and a crystal planeorientation of the second single-crystalline semiconductor layer aredifferent from each other.
 14. The semiconductor device according toclaim 13, wherein a conductivity type of the first field-effecttransistor is an n-type and a conductivity type of the secondfield-effect transistor is a p-type.
 15. The semiconductor deviceaccording to claim 13, wherein the crystal plane orientation of thefirst single-crystalline semiconductor layer is a {100} plane and thecrystal plane orientation of the second semiconductor layer is a {110}plane.
 16. The semiconductor device according to claim 15, wherein acrystal axis of a channel length direction of the firstsingle-crystalline semiconductor layer is <100> and a crystal axis of achannel length direction of the second single-crystalline semiconductorlayer is <110>.
 17. The semiconductor device according to claim 13,wherein the first single-crystalline semiconductor layer and the secondsingle-crystalline semiconductor layer are overlapped with each otherwith the planarization layer interposed therebetween, and the firstfield-effect transistor and the second field-effect transistor areelectrically connected to each other by a wiring which is formed in anopening which penetrates the second single-crystalline semiconductorlayer, the planarization layer, and the first gate insulating layer andreaches the first single-crystalline semiconductor layer.
 18. Thesemiconductor device according to claim 13, wherein the insulatingsubstrate is a glass substrate.
 19. A semiconductor device comprising:an insulating substrate; a first field-effect transistor over theinsulating substrate, the first field-effect transistor comprising: afirst single-crystalline semiconductor layer; a first gate insulatinglayer; and a first gate electrode layer; a planarization layer over thefirst field-effect transistor; and a second field-effect transistor overthe planarization layer, the second field-effect transistor comprising:a second single-crystalline semiconductor layer; a second gateinsulating layer; and a second gate electrode layer, wherein a crystalplane orientation of the first single-crystalline semiconductor layerand a crystal plane orientation of the second single-crystallinesemiconductor layer are same, and wherein a crystal axis of a channellength direction of the first single-crystalline semiconductor layer anda crystal axis of a channel length direction of the secondsingle-crystalline semiconductor layer are different from each other.20. The semiconductor device according to claim 19, wherein aconductivity type of the first field-effect transistor is an n-type anda conductivity type of the second field-effect transistor is a p-type.21. The semiconductor device according to claim 19, wherein the crystalplane orientations of the first single-crystalline semiconductor layerand the second semiconductor layer are {100} planes.
 22. Thesemiconductor device according to claim 21, wherein a crystal axis of achannel length direction of the first single-crystalline semiconductorlayer is <100> and a crystal axis of a channel length direction of thesecond single-crystalline semiconductor layer is <110>.
 23. Thesemiconductor device according to claim 19, wherein the firstsingle-crystalline semiconductor layer and the second single-crystallinesemiconductor layer are overlapped with each other with theplanarization layer interposed therebetween, and the first field-effecttransistor and the second field-effect transistor are electricallyconnected to each other by a wiring which is formed in an opening whichpenetrates the second single-crystalline semiconductor layer, theplanarization layer, and the first gate insulating layer and reaches thefirst single-crystalline semiconductor layer.
 24. The semiconductordevice according to claim 19, wherein the insulating substrate is aglass substrate.
 25. A method for manufacturing a semiconductor device,comprising the steps of: forming a first fragile layer in a firstsingle-crystalline semiconductor substrate by ion irradiation; bondingthe first single-crystalline semiconductor substrate over an insulatingsubstrate; separating the first single-crystalline semiconductorsubstrate at the first fragile layer so that a first single-crystallinesemiconductor layer is formed over the insulating substrate; forming afirst field-effect transistor using the first single-crystallinesemiconductor layer; forming a planarization layer over the firstfield-effect transistor; forming a second fragile layer in a secondsingle-crystalline semiconductor substrate by ion irradiation; bondingthe second single-crystalline semiconductor substrate over theplanarization layer; separating the second single-crystallinesemiconductor substrate at the second fragile layer so that a secondsingle-crystalline semiconductor layer is formed over the planarizationlayer; and forming a second field-effect transistor using thesingle-crystalline second semiconductor layer.
 26. The method formanufacturing a semiconductor device according to claim 25, wherein aconductivity type of the first field-effect transistor is an n-type anda conductivity type of the second field-effect transistor is a p-type.27. The method for manufacturing a semiconductor device according toclaim 25, wherein a crystal plane orientation of a plane of the firstsingle-crystalline semiconductor layer is a {100} plane and a crystalplane orientation of a plane of the second semiconductor layer is a{110} plane.
 28. The method for manufacturing a semiconductor deviceaccording to claim 27, wherein a crystal axis of a channel lengthdirection of the first single-crystalline semiconductor layer is <100>and a crystal axis of a channel length direction of the secondsingle-crystalline semiconductor layer is <110>.
 29. The method formanufacturing a semiconductor device according to claim 25, wherein thefirst single-crystalline semiconductor layer and the secondsingle-crystalline semiconductor layer are overlapped with each otherwith the planarization layer interposed therebetween, and the firstfield-effect transistor and the second field-effect transistor areelectrically connected to each other by a wiring which is formed in anopening which penetrates the second single-crystalline semiconductorlayer, the planarization layer, and the first gate insulating layer andreaches the first single-crystalline semiconductor layer.
 30. The methodfor manufacturing a semiconductor device according to claim 25, whereinthe insulating substrate is a glass substrate.